IBM Intel Xeon E5504 46D1351 User Manual

IBM

Product codes

46D1351

Intel® Xeon® Processor 5500 Series Datasheet, Volume 2

81

Register Description

2.12.2

TAD_INTERLEAVE_LIST_0

TAD_INTERLEAVE_LIST_1

TAD_INTERLEAVE_LIST_2

TAD_INTERLEAVE_LIST_3

TAD_INTERLEAVE_LIST_4

TAD_INTERLEAVE_LIST_5

TAD_INTERLEAVE_LIST_6

TAD_INTERLEAVE_LIST_7

TAD DRAM package assignments. When the corresponding DRAM_RULE hits, a 3-bit
number (determined by mode) is used to index into the Interleave_List Branches to
determine which channel the DRAM request belongs to.

Device:

3

Function: 1

Offset:

C0h, C4h, C8h, CCh, D0h, D4h, D8h, DCh

Access as a Dword

Bit

Type

Reset

Value

Description

29:28

RW

-

Logical Channel7. Index 111 of the Interleave List. Bits determined from

the matching TAD_DRAM_RULE mode.

00 – Logical channel 0
01 – Logical channel 1
10 – Logical channel 2
11 – Reserved

25:24

RW

-

Logical Channel6. Index 110 of the Interleave List. Bits determined from

the matching TAD_DRAM_RULE mode.

00 – Logical channel 0
01 – Logical channel 1
10 – Logical channel 2
11 – Reserved

21:20

RW

-

Logical Channel5. Index 101 of the Interleave List. Bits determined from

the matching TAD_DRAM_RULE mode.

00 – Logical channel 0
01 – Logical channel 1
10 – Logical channel 2
11 – Reserved

17:16

RW

-

Logical Channel4. Index 100 of the Interleave List. Bits determined from

the matching TAD_DRAM_RULE mode.

00 – Logical channel 0
01 – Logical channel 1
10 – Logical channel 2
11 – Reserved

13:12

RW

-

Logical Channel3. Index 011 of the Interleave List. Bits determined from

the matching TAD_DRAM_RULE mode.

00 – Logical channel 0
01 – Logical channel 1
10 – Logical channel 2
11 – Reserved