Intel X5460 AT80574KJ087N Data Sheet

101

While in the Stop-Grant state, SMI#, INIT#, BINIT# and LINT[1:0] will be latched by 
the processor, and only serviced when the processor returns to the Normal state. Only 
one occurrence of each event will be recognized upon return to the Normal state.

While in Stop-Grant state, the processor will process snoops on the front side bus and it 
will latch interrupts delivered on the front side bus.

The PBE# signal can be driven when the processor is in Stop-Grant state. PBE# will be 
asserted if there is any pending interrupt latched within the processor. Pending 
interrupts that are blocked by the EFLAGS.IF bit being clear will still cause assertion of 
PBE#. Assertion of PBE# indicates to system logic that it should return the processor to 
the Normal state.

The Extended HALT Snoop state is used in conjunction with the Extended HALT state. If 
the Extended HALT state is not enabled in the BIOS, the default Snoop state entered 
will be the HALT Snoop state. Refer to the sections below for details on HALT Snoop 
state, Stop Grant Snoop state and Extended HALT Snoop state.

The processor will respond to snoop or interrupt transactions on the front side bus 
while in Stop-Grant state or in HALT state. During a snoop or interrupt transaction, the 
processor enters the HALT/Grant Snoop state. The processor will stay in this state until 
the snoop on the front side bus has been serviced (whether by the processor or another 
agent on the front side bus) or the interrupt has been latched. After the snoop is 
serviced or the interrupt is latched, the processor will return to the Stop-Grant state or 
HALT state, as appropriate.

The Extended HALT Snoop state is the default Snoop state when the Extended HALT 
state is enabled via the BIOS. The processor will remain in the lower bus to core 
frequency ratio and VID operating point of the Extended HALT state. 

While in the Extended HALT Snoop state, snoops and interrupt transactions are handled 
the same way as in the HALT Snoop state. After the snoop is serviced or the interrupt is 
latched, the processor will return to the Extended HALT state.

Quad-Core Intel® Xeon® Processor 5400 Series supports Enhanced Intel SpeedStep

® 

Technology. This technology enables the processor to switch between multiple 
frequency and voltage points, which results in platform power savings. Enhanced Intel 
SpeedStep

 

Technology requires support for dynamic VID transitions in the platform. 

Switching between voltage/frequency states is software controlled. For more 
configuration details also refer to the Intel® 64 and IA-32 Architectures Software 
Developer’s Manual.

Not all Quad-Core Intel® Xeon® Processor 5400 Series are capable of supporting 

Enhanced Intel SpeedStep Technology. More details on which processor frequencies will 

support this feature will be provided in the Quad-Core Intel® Xeon® Processor 5400 

Series Specification Update.