Intel Xeon E5440 BX80574E5440 Data Sheet

77

RSP#

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RSP# (Response Parity) is driven by the response agent (the agent 

responsible for completion of the current transaction) during 

assertion of RS[2:0]#, the signals for which RSP# provides parity 

protection. It must connect to the appropriate pins of all processor 

FSB agents.
A correct parity signal is high if an even number of covered signals 

are low and low if an odd number of covered signals are low. While 

RS[2:0]# = 000, RSP# is also high, since this indicates it is not being 

driven by any agent guaranteeing correct parity.

3

SKTOCC#

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SKTOCC# (Socket occupied) will be pulled to ground by the processor 

to indicate that the processor is present. There is no connection to 

the processor silicon for this signal.

SMI#

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SMI# (System Management Interrupt) is asserted asynchronously by 

system logic. On accepting a System Management Interrupt, 

processors save the current state and enter System Management 

Mode (SMM). An SMI Acknowledge transaction is issued, and the 

processor begins program execution from the SMM handler.
If SMI# is asserted during the deassertion of RESET# the processor 

will tri-state its outputs. See 

2

STPCLK#

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STPCLK# (Stop Clock), when asserted, causes processors to enter a 

low power Stop-Grant state. The processor issues a Stop-Grant 

Acknowledge transaction, and stops providing internal clock signals 

to all processor core units except the FSB and APIC units. The 

processor continues to snoop bus transactions and service interrupts 

while in Stop-Grant state. When STPCLK# is deasserted, the 

processor restarts its internal clock to all units and resumes 

execution. The assertion of STPCLK# has no effect on the bus clock; 

STPCLK# is an asynchronous input.

2

TCK

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TCK (Test Clock) provides the clock input for the processor Test Bus 

(also known as the Test Access Port).

TDI

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TDI (Test Data In) transfers serial test data into the processor. TDI 

provides the serial input needed for JTAG specification support.

TDO

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TDO (Test Data Out) transfers serial test data out of the processor. 

TDO provides the serial output needed for JTAG specification support.

TESTHI[12:10]

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TESTHI[12:10] must be connected to a V

TT

 power source through a 

resistor for proper processor operation. Refer to 

 for 

TESTHI grouping restrictions.

TESTIN1
TESTIN2

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TESTIN1 must be connected to a VTT power source through a resistor 

as well as to the TESTIN2 land of the same socket for proper 

processor operation.
TESTIN2 must be connected to a VTT power source through a resistor 

as well as to the TESTIN1 land of the same socket for proper 

processor operation.

THERMTRIP#

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Assertion of THERMTRIP# (Thermal Trip) indicates the processor 

junction temperature has reached a temperature beyond which 

permanent silicon damage may occur. Measurement of the 

temperature is accomplished through an internal thermal sensor. 

Upon assertion of THERMTRIP#, the processor will shut off its internal 

clocks (thus halting program execution) in an attempt to reduce the 

processor junction temperature. To protect the processor its core 

voltage (V

CC

) must be removed following the assertion of 

THERMTRIP#. Intel also recommends the removal of V

TT

 when 

THERMTRIP# is asserted.
Driving of the THERMTRIP# signals is enabled within 10 μs of the 

assertion of PWRGOOD and is disabled on de-assertion of PWRGOOD. 

Once activated, THERMTRIP# remains latched until PWRGOOD is de-

asserted. While the de-assertion of the PWRGOOD signal will de-

assert THERMTRIP#, if the processor’s junction temperature remains 

at or above the trip level, THERMTRIP# will again be asserted within 

10 μs of the assertion of PWRGOOD.

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