Partner Tech pt-5700 User Manual
Advanced BIOS Features
25
DRAM Clock
This item enables you to manually set the DRAM Clock to 200 MHz. We recommend that you leave this item at the
default value. The default value is By SPD.
default value. The default value is By SPD.
DRAM Timing
Set this to the default value to enable the system to automatically set the SDRAM timing by SPD (Serial Presence
Detect). SPD is an EEPROM chip on the DIMM module that stores information about the memory chips it contains,
including size, speed, voltage, row and column addresses, and manufacturer. The default value is By SPD.
Detect). SPD is an EEPROM chip on the DIMM module that stores information about the memory chips it contains,
including size, speed, voltage, row and column addresses, and manufacturer. The default value is By SPD.
SDRAM CAS Latency
This item enables you to specify the time delay (in clock cycles or CLKs) that elapses before the SDRAM carries out a
read command after receiving it. The value specified here also sets the number of CLKs that will elapse for the com-
pletion of the first part of a burst transfer. Low values indicate a faster data transaction. When synchronous DRAM is
installed, the number of clock cycles of CAS latency depends on the DRAM timing. The default is 2.5.
read command after receiving it. The value specified here also sets the number of CLKs that will elapse for the com-
pletion of the first part of a burst transfer. Low values indicate a faster data transaction. When synchronous DRAM is
installed, the number of clock cycles of CAS latency depends on the DRAM timing. The default is 2.5.
Bank Interleave
Enable this item to increase memory speed. When enabled, separate memory banks are set for odd and even addresses
and the next byte of memory can be accessed while the current byte is being refreshed. The default is Disabled.
and the next byte of memory can be accessed while the current byte is being refreshed. The default is Disabled.
Precharge to Active(Trp)
This item is used to designate the minimum Row Precharge time of the SDRAM devices on the module. DRAM must
continually be refreshed or it will lose its data. Normally, DRAM is refreshed entirely as the result of a single request.
This option allows you to determine the number of CPU clocks allocated for the Row Address Strobe (RAS) to accu-
mulate its charge before the DRAM is refreshed. If insufficient time is allowed, refresh may be incomplete and data
lost. The default is 3T.
continually be refreshed or it will lose its data. Normally, DRAM is refreshed entirely as the result of a single request.
This option allows you to determine the number of CPU clocks allocated for the Row Address Strobe (RAS) to accu-
mulate its charge before the DRAM is refreshed. If insufficient time is allowed, refresh may be incomplete and data
lost. The default is 3T.
Active to Precharge(Tras)
This item specifies the number of clock cycles needed after a bank active command before a precharge can occur. The
default is 6T.
default is 6T.
Active to CMD(Trcd)
This item specifies the minimum required delay between activation of different rows. The default is 3T.
REF to ACT/REF (Trfc)
Set REP to ACT / REF to 21T (Default value:21T)
Act 0 to Act 1 (TRRD)
Set ACT(0) to ACT(1) to 3T(Default value:3T)
DRAM Command Rate
This item enables you to specify the waiting time for the CPU to issue the next command after issuing the command to
the DDR memory. We recommend that you leave this item at the default value. The default value is 2T Command
the DDR memory. We recommend that you leave this item at the default value. The default value is 2T Command
RDSAIT mode
Auto: Auto detect RDSAIT mode. (Default value)
Manual: Set RDSAIT mode by manually.
NOTE
When the DRAM Timing setting is set to “Manual” the fields that previously had an “x”
before them become available.
before them become available.