Partner Tech pt-5700 User Manual
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Chapter 3 BIOS Setup Utility
Figure 3.7
CPU & PCI Bus Control menu
PCI Master 0 WS Write
When enabled, writes to the PCI bus are executed with zero wait states. The default setting is Enabled.
PCI Delay Transaction
The mainboard’s chipset has an embedded 32-bit post write buffer to support delay transactions cycles. Select Enabled
to support compliance with PCI specification version 2.1. The default setting is Enabled.
to support compliance with PCI specification version 2.1. The default setting is Enabled.
VLink mode selection
This menu item controls the data transfer speed between the north and south bridge.
By Auto: VLink mode selection by automatically. (Default value)
Mode 0: Set VLink mode to mode 0.
Mode 1: Set VLink mode to mode 1.
VLink 8X Support
Disabled: Disabled VLink 8x support.
Enabled: Enabled VLink 8x support.(Default value)
DRDY_Timing
Default: Set default to DRDY_Timing.(Default value)
Slowest: Set slowest to DRDY_Timing.
Optimize: Set optimize to DRDY_Timing.