Intel Celeron 1.40GHz RK80530RY017256 Data Sheet

22

open drain and should be pulled high to V

CCCMOS

. This ensures not only correct operation for 

current Intel Celeron processors, but compatibility for future Intel Celeron processor products as 
well.

The groups and the signals contained within each group are shown in 

. Refer to 

for descriptions of these signals.

1. See 

 for information on the PWRGOOD signal.

2. See 

 for information on the SLP# signal.

3. See 

 for information on the THERMTRIP# signal.

4. These signals are specified for 2.5 V operation for S.E.P.P. and PPGA packages; they are specified at 1.5V 

operation for the FC-PGA/FC-PGA2 packages.

5. V

CCCORE

 is the power supply for the processor core.

VID[4:0] and VID[3:0] are described in 

V

TT

 is used to terminate the system bus and generate V

REF

 on the processor substrate.

V

SS

 is system ground.

V

CC5

 is not connected to the Celeron processor. This supply is used for Voltage Transient Tools.

SLOTOCC# is described in 

BSEL is described in 

.

EMI pins are described in 

.

V

CCL2

 is a Pentium

®

 II processor reserved signal provided to maintain compatibility with the Pentium

®

 II 

processor and may be left as a no-connect for “Intel Celeron processor-only” designs. 

6. Only applies to Intel Celeron processors in the S.E.P. Package.
7. Only applies to Intel Celeron processors in the PPGA and FC-PGA/FC-PGA2 packages. 
8. The BR0# pin is the only BREQ# signal that is bidirectional. See 

for more information.

9. These signals are specified for 2.5 V operation. 

10.BSEL1 is not used in Celeron processors.

11. RESET# must always be terminated to V

TT

 on the motherboard for PGA packages. On-die termination is not 

provided for this signal on FC-PGA/FC-PGA2 packages.

12.For the FC-PGA/FC-PGA2 packages, this signal is used to control the value of the processor on-die 

termination resistance. Refer to the specific platform design guide for the recommended pull-down resistor 
value.

13.Only applies to Intel Celeron processors in the FC-PGA/FC-PGA2 packages.
14.S.E.P. Package and FC-PGA/FC-PGA2 packages.

AGTL+ Input

BPRI#, DEFER#, RESET#

11

, RS[2:0]#, TRDY#

AGTL+ Output

PRDY#

AGTL+ I/O

A[31:3]#, ADS#, BNR#, BP[3:2]#, BPM[1:0]#, BR0#

8

, D[63:0]#, DBSY#, DRDY#, HIT#, 

HITM#, LOCK#, REQ[4:0]#, 

CMOS Input

4

A20M#, FLUSH#, IGNNE#, INIT#, LINT0/INTR, LINT1/NMI, PREQ#, SMI#, SLP#

2

, 

STPCLK#

CMOS Input

PWRGOOD

1,9

CMOS Output

4

FERR#, IERR#, THERMTRIP#

3

System Bus Clock

BCLK

9

APIC Clock

PICCLK

9

APIC I/O

4

PICD[1:0]

TAP Input

4

TCK, TDI, TMS, TRST#

TAP Output

4

TDO

Power/Other

5

CPUPRES#

7

, EDGCTRL

7

, EMI

6

, PLL[2:1]

7

, SLOTOCC#

6

, THERMDP, THERMDN, 

V

CC1.5

7

, V

CC2.5

7

, V

CCL2

5

, V

CC5

6

, V

CCCMOS

7

, V

CCCORE

, V

COREDET

7

, VID[3:0]

7

, 

VID[4:0]

6

, V

REF

[7:0]

7

, V

SS

, V

TT

14

, RTTCTRL

12

, BSEL[1:0]

10

, SLEWCTRL

13