Intel Celeron 1.40GHz RK80530RY017256 Data Sheet

3

Introduction....................................................................................................................... 11

Terminology......................................................................................................... 11
1.1.1

Package Terminology............................................................................. 12

Processor Naming Convention...............................................................13

Electrical Specifications.................................................................................................... 15

System Bus and Vref........................................................................................... 15

Clock Control and Low Power States.................................................................. 15
2.2.1

Normal State—State 1 ........................................................................... 16

AutoHALT Power Down State—State 2 ................................................. 16

Stop-Grant State—State 3 .....................................................................17

HALT/Grant Snoop State—State 4 ........................................................ 17

Sleep State—State 5.............................................................................. 17

Deep Sleep State—State 6 .................................................................... 18

Clock Control.......................................................................................... 18

Power and Ground Pins ...................................................................................... 18
2.3.1

Processor Decoupling .........................................................................................19
2.4.1

System Bus AGTL+ Decoupling............................................................. 19

Voltage Identification ........................................................................................... 20

System Bus Unused Pins.................................................................................... 21

Processor System Bus Signal Groups ................................................................ 21
2.7.1

Asynchronous Vs. Synchronous for System Bus Signals ...................... 23

System Bus Frequency Select Signal (BSEL[1:0])................................. 23

Test Access Port (TAP) Connection.................................................................... 23

Maximum Ratings................................................................................................ 23

Processor DC Specifications............................................................................... 24

AGTL+ System Bus Specifications .....................................................................33

System Bus AC Specifications ............................................................................34

System Bus Signal Simulations........................................................................................ 52

System Bus Clock (BCLK) Signal Quality Specifications and 
Measurement Guidelines .................................................................................... 52

AGTL+ Signal Quality Specifications and Measurement Guidelines ..................55

Non-AGTL+ Signal Quality Specifications and Measurement Guidelines...........57
3.3.1

Overshoot/Undershoot Guidelines ......................................................... 57

Ringback Specification ........................................................................... 58

Settling Limit Guideline........................................................................... 59

AGTL+ Signal Quality Specifications and Measurement Guidelines 
(FC-PGA/FC-PGA2 Packages) ........................................................................... 59
3.4.1

Overshoot/Undershoot Guidelines (FC-PGA/FC-PGA2 Packages) ....... 59

Overshoot/Undershoot Magnitude (FC-PGA/FC-PGA2 Packages) ....... 59

Overshoot/Undershoot Pulse Duration (FC-PGA/FC-PGA2 
Packages) .............................................................................................. 60

Activity Factor (FC-PGA/FC-PGA2 Packages) ...................................... 60