Intel Celeron 1.40GHz RK80530RY017256 Data Sheet
Product codes
RK80530RY017256
46
Datasheet
Intel
®
Celeron
®
Processor up to 1.10 GHz
NOTES:
1. Unless otherwise noted, all specifications in this table apply to all Celeron processor frequencies.
2. For the S.E.P. and PPGA packages: All AC timings for the TAP signals are referenced to the TCK rising edge
2. For the S.E.P. and PPGA packages: All AC timings for the TAP signals are referenced to the TCK rising edge
at 1.25 V at the processor core pins. All TAP signal timings (TMS, TDI, etc.) are referenced at 1.25 V at the
processor core pins.
For the FC-PGA/FC-PGA2 packages: All AC timings for the TAP signals are referenced to the TCK rising
edge at 0.75 V at the processor pins. All TAP signal timings (TMS, TDI, etc.) are referenced at 0.75 V at the
processor pins.
processor core pins.
For the FC-PGA/FC-PGA2 packages: All AC timings for the TAP signals are referenced to the TCK rising
edge at 0.75 V at the processor pins. All TAP signal timings (TMS, TDI, etc.) are referenced at 0.75 V at the
processor pins.
3. These specifications are tested during manufacturing, unless otherwise noted.
4. 1 ns can be added to the maximum TCK rise and fall times for every 1 MHz below 16.667 MHz.
5. Referenced to TCK rising edge.
6. Referenced to TCK falling edge.
7. For the S.E.P. and PPGA packages: Valid delay timing for this signal is specified to 2.5 V +5%.
4. 1 ns can be added to the maximum TCK rise and fall times for every 1 MHz below 16.667 MHz.
5. Referenced to TCK rising edge.
6. Referenced to TCK falling edge.
7. For the S.E.P. and PPGA packages: Valid delay timing for this signal is specified to 2.5 V +5%.
For the FC-PGA/FC-PGA2 packages: Valid delay timing for this signal is specified to 1.5 V +3%.
8. Non-Test Outputs and Inputs are the normal output or input signals (besides TCK, TRST#, TDI, TDO, and
TMS). These timings correspond to the response of these signals due to TAP operations.
9. During Debug Port operation, use the normal specified timings rather than the TAP signal timings.
10.Not 100% tested. Specified by design characterization.
Table 26. System Bus AC Specifications (TAP Connection) at the Processor Core Pins
(for Both S.E.P. and PPGA Packages)
T# Parameter
Min
Max
Unit
Figure
Notes
T30: TCK Frequency
16.667
MHz
T31: TCK Period
60.0
ns
T32: TCK High Time
25.0
ns
@1.7 V; 10
T33: TCK Low Time
25.0
ns
@0.7 V; 10
T34: TCK Rise Time
5.0
ns
(0.7 V–1.7 V);
4, 10
T35: TCK Fall Time
5.0
ns
(1.7 V–0.7 V)
;
4, 10
T36: TRST# Pulse Width
40.0
ns
Asynchronous; 10
T37: TDI, TMS Setup Time
5.0
ns
5
T38: TDI, TMS Hold Time
14.0
ns
5
T39: TDO Valid Delay
1.0
10.0
ns
6, 7
T40: TDO Float Delay
25.0
ns
6, 7, 10
T41: All Non-Test Outputs Valid Delay
2.0
25.0
ns
6, 8, 9
T42: All Non-Test Inputs Setup Time
25.0
ns
6, 8, 9, 10
T43: All Non-Test Inputs Setup Time
5.0
ns
5, 8, 9
T44: All Non-Test Inputs Hold Time
13.0
ns
5, 8, 9