Intel Celeron 1.40GHz RK80530RY017256 Data Sheet

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Settling limit defines the maximum amount of ringing at the receiving pin that a signal must reach 
before its next transition. The amount allowed is 10 percent of the total signal swing (V

HI 

–

 V

LO

) 

above and below its final value. A signal should be within the settling limits of its final value, when 
either in its high state or low state, before it transitions again.

Signals that are not within their settling limit before transitioning are at risk of unwanted 
oscillations which could jeopardize signal integrity. Simulations to verify settling limit may be 
done either with or without the input protection diodes present. Violation of the settling limit 
guideline is acceptable if simulations of 5 to 10 successive transitions do not show the amplitude of 
the ringing increasing in the subsequent transitions.

Overshoot (or undershoot) is the absolute value of the maximum voltage above the nominal high 
voltage or below V

SS

. The overshoot guideline limits transitions beyond V

CC

 or V

SS

 due to the fast 

signal edge rates. The processor can be damaged by repeated overshoot events on 1.5 V or 2.5 V 
tolerant buffers if the charge is large enough (i.e., if the overshoot is great enough). Determining 
the impact of an overshoot/undershoot condition requires knowledge of the magnitude, the pulse 
direction and the activity factor (AF). Permanent damage to the processor is the likely result of 
excessive overshoot/undershoot. Violating the overshoot/undershoot guideline will also make 
satisfying the ringback specification difficult. 

When performing simulations to determine impact of overshoot and overshoot, ESD diodes must 
be properly characterized. ESD protection diodes do not act as voltage clamps and will not provide 
overshoot or undershoot protection. ESD diodes modeled within Intel I/O Buffer models do not 
clamp undershoot or overshoot and will yield correct simulation results. If other I/O buffer models 
are being used to characterize the FC-PGA/FC-PGA2 processor performance, care must be taken 
to ensure that ESD models do not clamp extreme voltage levels. Intel I/O Buffer models also 
contain I/O capacitance characterization. Therefore, removing the ESD diodes from an I/O Buffer 
model will impact results and may yield excessive overshoot/undershoot. 

Magnitude describes the maximum potential difference between a signal and its voltage reference 
level, V

SS

 (overshoot) and V

TT

 (undershoot). While overshoot can be measured relative to V

SS

 

using one probe (probe to signal and GND lead to V

SS

), undershoot must be measured relative to 

V

TT

. This can be accomplished by simultaneously measuring the V

TT

 plane while measuring the 

signal undershoot. Today’s oscilloscopes can easily calculate the true undershoot waveform using a 
Math function where the Signal waveform is subtracted from the V

TT

 waveform. The true 

undershoot waveform can also be obtained with the following oscilloscope data file analysis:

Converted Undershoot Waveform = 

V

TT

– Signal_measured

The converted undershoot waveform appears as a positive (overshoot) signal.

Overshoot (rising edge) and undershoot (falling edge) conditions are separate and their impact 
must be determined independently.