Kingston Technology 3GB, 1800MHz, DDR3, Non-ECC, CL9 (9-9-9-27), DIMM, (Kit of 3), XMP Tall HS KHX1800C9D3T1K3/3GX Data Sheet
Product codes
KHX1800C9D3T1K3/3GX
Memory Module Specifications
KHX1800C9D3T1K3/3GX
3GB (1GB 128M x 64-Bit x 3 pcs.) DDR3-1800MHz
CL9 240-Pin DIMM Kit
CL9 240-Pin DIMM Kit
Kingston.com
Document No. 4805272-001.B00 07/18/11 Page 1
DESCRIPTION
Kingston’s KHX1800C9D3T1K3/3GX is a kit of three
128M x 64-bit 1GB (1024MB) DDR3-1800MHz CL9
SDRAM (Synchronous DRAM) memory modules, based
on eight 128M x 8-bit DDR3 FBGA components per
module. Each module kit supports Intel
128M x 64-bit 1GB (1024MB) DDR3-1800MHz CL9
SDRAM (Synchronous DRAM) memory modules, based
on eight 128M x 8-bit DDR3 FBGA components per
module. Each module kit supports Intel
®
XMP (Extreme
Memory Profiles). Total kit capacity is 3GB. Each module
kit has been tested to run at DDR3-1800MHz at a low
latency timing of 9-9-9-27 at 1.65V. The SPDs are pro-
grammed to JEDEC standard latency DDR3-1333MHz
timing of 9-9-9 at 1.5V. Each 240-pin DIMM uses gold
contact fingers and requires +1.5V. The JEDEC standard
electrical and mechanical specifications are as follows:
kit has been tested to run at DDR3-1800MHz at a low
latency timing of 9-9-9-27 at 1.65V. The SPDs are pro-
grammed to JEDEC standard latency DDR3-1333MHz
timing of 9-9-9 at 1.5V. Each 240-pin DIMM uses gold
contact fingers and requires +1.5V. The JEDEC standard
electrical and mechanical specifications are as follows:
SPECIFICATIONS
CL(IDD)
9 cycles
Row Cycle Time (tRCmin)
49.5ns (min.)
Refresh to Active/Refresh
110ns
Command Time (tRFCmin)
Row Active Time (tRASmin)
36ns (min.)
Power
1.080 W (operating per module)
UL Rating
94 V - 0
Operating Temperature
0° C to 85° C
Storage Temperature
-55° C to +100° C
FEATURES
• JEDEC standard 1.5V ± 0.075V Power Supply
• VDDQ = 1.5V ± 0.075V
• 667MHz fCK for 1333Mb/sec/pin
• 8 independent internal bank
• Programmable CAS Latency: 5,6,7,8,9,10
• Posted CAS
• Programmable Additive Latency: 0, CL - 2, or CL - 1 clock
• Programmable CAS Write Latency(CWL) = 7(DDR3-1333)
• 8-bit pre-fetch
• Burst Length: 8 (Interleave without any limit, sequential with
• VDDQ = 1.5V ± 0.075V
• 667MHz fCK for 1333Mb/sec/pin
• 8 independent internal bank
• Programmable CAS Latency: 5,6,7,8,9,10
• Posted CAS
• Programmable Additive Latency: 0, CL - 2, or CL - 1 clock
• Programmable CAS Write Latency(CWL) = 7(DDR3-1333)
• 8-bit pre-fetch
• Burst Length: 8 (Interleave without any limit, sequential with
starting address “000” only), 4 with tCCD = 4 which does
not allow seamless read or write [either on the fly using A12
or MRS]
not allow seamless read or write [either on the fly using A12
or MRS]
• Bi-directional Differential Data Strobe
• Internal(self) calibration : Internal self calibration through ZQ
• Internal(self) calibration : Internal self calibration through ZQ
pin (RZQ : 240 ohm ± 1%)
• On Die Termination using ODT pin
• Average Refresh Period 7.8us at lower than TCASE 85°C,
• Average Refresh Period 7.8us at lower than TCASE 85°C,
3.9us at 85°C < TCASE ≤ 95°C
• Asynchronous Reset
• PCB : Height 2.401” (61.00mm) w/ heatsink, single sided
• PCB : Height 2.401” (61.00mm) w/ heatsink, single sided
component
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