Intel E5540 AT80602000789AA User Manual

Intel

®

 Xeon

®

 Processor 5500 Series Datasheet, Volume 1

123

Note that the 4-byte data response defined above is sent in standard PECI ordering 
with LSB first and MSB last.

The MbxSend() command is used to acquire control of the PECI mailbox and issue 
information regarding the specific request. The completion code response indicates 
whether or not the originator has acquired a lock on the mailbox, and that completion 
code always specifies the Transaction ID associated with that lock (see 

). 

Once a mailbox has been acquired by an originating agent, future requests to acquire 
that mailbox will be denied with an ‘interface busy’ completion code response.

The lock on a mailbox is not achieved until the last bit of the MbxSend() Read FCS is 
transferred (in other words, it is not committed until the command completes). If the 
host aborts the command at any time prior to that bit transmission, the mailbox lock 
will be lost and it will remain available for any other agent to take control.

 Response Data[31:0]

Byte #

Byte 

Definition

0

Client Address

1

Write Length

0x02

2

Read Length

0x05

10

FCS

3

Cmd Code

0xd5

11

Completion

Code

5

6

LSB

MSB

5

6

4

Transaction ID

10

11

5

6

8

9

7

10

FCS

11

Aborted Write FCS Response data is not ready. Command retry is appropriate.

CC: 0x40

Command passed, data is valid

CC: 0x80

Error causing a response timeout. Either due to a rare, internal timing condition or a 

processor RESET condition or processor S1 state. Retry is appropriate outside of the 

RESET or S1 states.

CC: 0x81

Thermal configuration data was malformed or exceeded limits.

CC: 0x82

Thermal status mask is illegal

CC: 0x83

Invalid counter select

CC: 0x84

Invalid Machine Check Bank or Index

CC: 0x85

Failure due to lack of Mailbox lock or invalid Transaction ID

CC: 0x86

Mailbox interface is unavailable or busy

CC: 0xFF

Unknown/Invalid Mailbox Request