Intel Pentium 4 RK80532PC033512 User Manual
Product codes
RK80532PC033512
Intel
®
Pentium
®
4 Processor in the 423-pin Package
67
INIT#
Input
INIT# (Initialization), when asserted, resets integer registers inside the processor
without affecting its internal caches or floating-point registers. The processor then
begins execution at the power-on Reset vector configured during power-on
configuration. The processor continues to handle snoop requests during INIT#
assertion. INIT# is an asynchronous signal and must connect the appropriate pins
of all processor system bus agents.
without affecting its internal caches or floating-point registers. The processor then
begins execution at the power-on Reset vector configured during power-on
configuration. The processor continues to handle snoop requests during INIT#
assertion. INIT# is an asynchronous signal and must connect the appropriate pins
of all processor system bus agents.
If INIT# is sampled active on the active to inactive transition of RESET#, then the
processor executes its Built-in Self-Test (BIST).
processor executes its Built-in Self-Test (BIST).
ITP_CLK[1:0]
Input
ITP_CLK[1:0] are copies of BCLK that are used only in processor systems where
no debug port is implemented on the system board. ITP_CLK[1:0] are used as
BCLK[1:0] references for a debug port implemented on an interposer. If a debug
port is implemented in the system, ITP_CLK[1:0] are no connects in the system.
These are not processor signals.
no debug port is implemented on the system board. ITP_CLK[1:0] are used as
BCLK[1:0] references for a debug port implemented on an interposer. If a debug
port is implemented in the system, ITP_CLK[1:0] are no connects in the system.
These are not processor signals.
LINT[1:0]
Input
LINT[1:0] (Local APIC Interrupt) must connect the appropriate pins of all APIC Bus
agents. When the APIC is disabled, the LINT0 signal becomes INTR, a maskable
interrupt request signal, and LINT1 becomes NMI, a nonmaskable interrupt. INTR
and NMI are backward compatible with the signals of those names on the Pentium
processor. Both signals are asynchronous.
agents. When the APIC is disabled, the LINT0 signal becomes INTR, a maskable
interrupt request signal, and LINT1 becomes NMI, a nonmaskable interrupt. INTR
and NMI are backward compatible with the signals of those names on the Pentium
processor. Both signals are asynchronous.
Both of these signals must be software configured via BIOS programming of the
APIC register space to be used either as NMI/INTR or LINT[1:0]. Because the APIC
is enabled by default after Reset, operation of these pins as LINT[1:0] is the default
configuration.
APIC register space to be used either as NMI/INTR or LINT[1:0]. Because the APIC
is enabled by default after Reset, operation of these pins as LINT[1:0] is the default
configuration.
LOCK#
Input/
Output
LOCK# indicates to the system that a transaction must occur atomically. This signal
must connect the appropriate pins of all processor system bus agents. For a locked
sequence of transactions, LOCK# is asserted from the beginning of the first
transaction to the end of the last transaction.
must connect the appropriate pins of all processor system bus agents. For a locked
sequence of transactions, LOCK# is asserted from the beginning of the first
transaction to the end of the last transaction.
When the priority agent asserts BPRI# to arbitrate for ownership of the processor
system bus, it will wait until it observes LOCK# deasserted. This enables symmetric
agents to retain ownership of the processor system bus throughout the bus locked
operation and ensure the atomicity of lock.
system bus, it will wait until it observes LOCK# deasserted. This enables symmetric
agents to retain ownership of the processor system bus throughout the bus locked
operation and ensure the atomicity of lock.
MCERR#
Input/
Output
MCERR# (Machine Check Error) is asserted to indicate an unrecoverable error
without a bus protocol violation. It may be driven by all processor system bus
agents.
without a bus protocol violation. It may be driven by all processor system bus
agents.
MCERR# assertion conditions are configurable at a system level. Assertion options
are defined by the following options:
are defined by the following options:
Enabled or disabled.
Asserted, if configured, for internal errors along with IERR#.
Asserted, if configured, by the request initiator of a bus transaction after it
observes an error.
Asserted by any bus agent when it observes an error in a bus
transaction.
For more details regarding machine check architecture, please refer to the IA-32
Software Developer’s Manual, Volume 3: System Programming Guide.
Software Developer’s Manual, Volume 3: System Programming Guide.
PROCHOT#
Output
PROCHOT# will go active when the processor temperature monitoring sensor
detects that the processor has reached its maximum tested operating temperature.
This indicates that the processor Thermal Control Circuit has been activated, if
enabled. See Section 7.3 for more details.
detects that the processor has reached its maximum tested operating temperature.
This indicates that the processor Thermal Control Circuit has been activated, if
enabled. See Section 7.3 for more details.
Table 32. Signal Description (Page 5 of 8)
Name
Type
Description