Intel Pentium III BX80525U550512E Data Sheet

3

Introduction......................................................................................................................... 9

Terminology......................................................................................................... 10
1.1.1

S.E.C.C.2 and S.E.C.C. Packaged Processor Terminology ..................10

Processor Naming Convention...............................................................11

Electrical Specifications.................................................................................................... 13

Processor System Bus and V

REF

........................................................................ 13

Clock Control and Low Power States.................................................................. 14
2.2.1

Normal State—State 1 ........................................................................... 15

AutoHALT Powerdown State—State 2................................................... 15

Stop-Grant State—State 3 .....................................................................15

HALT/Grant Snoop State—State 4 ........................................................ 16

Sleep State—State 5.............................................................................. 16

Deep Sleep State—State 6 .................................................................... 16

Clock Control.......................................................................................... 17

Power and Ground Pins ...................................................................................... 17

Decoupling Guidelines ........................................................................................ 17
2.4.1

CORE 

Decoupling............................................................ 18

Processor System Bus AGTL+ Decoupling............................................18

Processor System Bus Clock and Processor Clocking ....................................... 18

Voltage Identification ........................................................................................... 18

Processor System Bus Unused Pins................................................................... 20

Processor System Bus Signal Groups ................................................................ 20
2.8.1

Asynchronous vs. Synchronous for System Bus Signals ....................... 21

System Bus Frequency Select Signal (BSEL0)...................................... 22

Test Access Port (TAP) Connection.................................................................... 23

Maximum Ratings................................................................................................ 24

Processor DC Specifications............................................................................... 25

AGTL+ System Bus Specifications .....................................................................32

System Bus AC Specifications ............................................................................32

Signal Quality Specifications ............................................................................................ 40

BCLK, PICCLK, and PWRGOOD Signal Quality Specifications and 
Measurement Guidelines .................................................................................... 40

AGTL+ and Non-AGTL+ Overshoot/Undershoot Specifications and 
Measurement Guidelines .................................................................................... 41
3.2.1

Overshoot/Undershoot Magnitude ......................................................... 41

Overshoot/Undershoot Pulse Duration................................................... 42

Overshoot/Undershoot Activity Factor.................................................... 42