Intel E5506 AT80602000798AA User Manual
Product codes
AT80602000798AA
Intel® Xeon® Processors 5500 Series Electrical Specifications
40
Intel
®
Xeon
®
Processor 5500 Series Datasheet, Volume 1
Notes:
1.
Unless otherwise noted, all specifications in this table apply to all processor frequencies.
2.
V
IL
is the maximum voltage level at a receiving agent that will be interpreted as a logical low value.
3.
V
IH
is the minimum voltage level at a receiving agent that will be interpreted as a logical high value.
4.
V
IH
and V
OH
may experience excursions above V
DDQ
.
5.
This is the pull down driver resistance. Refer to processor signal integrity models for I/V characteristics.
6.
R
VTT_TERM
is the termination on the DIMM and not controlled by the Intel Xeon Processor 5500 Series.
Please refer to the applicable DIMM datasheet.
7.
The minimum and maximum values for these signals are programmable by BIOS to one of the pairs.
8.
COMP resistance must be provided on the system board with 1% resistors. DDR_COMP[2:0] resistors are
to Vss.
Note:
1.
V
TTD
supplies the PECI interface. PECI behavior does not affect V
TTD
min/max specifications.
2.
It is expected that the PECI driver will take into account, the variance in the receiver input thresholds and
consequently, be able to drive its output within safe limits (-0.150 V to 0.275*V
TTD
for the low level and
0.725*V
TTD
to V
TTD
+0.150 for the high level).
3.
The leakage specification applies to powered devices on the PECI bus.
4.
One node is counted for each client and one node for the system host. Extended trace lengths might appear
as additional nodes.
5.
Excessive capacitive loading on the PECI line may slow down the signal rise/fall times and consequently
limit the maximum bit rate at which the interface can operate.
6.
Please refer to
for further information.
I
LI
Input Leakage Current
N/A
N/A
± 500
mA
DDR_COMP0 COMP Resistance
99
100
101
Ω
8
DDR_COMP1 COMP Resistance
24.65
24.9
25.15
Ω
8
DDR_COMP2 COMP Resistance
128.7
130
131.3
Ω
8
Table 2-12. DDR3 Signal Group DC Specifications (Sheet 2 of 2)
Symbol
Parameter
Min
Typ
Max
Units
Notes
1
Table 2-13. PECI DC Electrical Limits
Symbol
Definition and Conditions
Min
Max
Units
Notes
1
V
In
Input Voltage Range
-0.150
V
TTD
+ 0.150
V
V
Hysteresis
Hysteresis
0.100 * V
TTD
V
V
N
Negative-edge threshold voltage
0.275 * V
TTD
0.500 * V
TTD
V
2,6
V
P
Positive-edge threshold voltage
0.550 * V
TTD
0.725 * V
TTD
V
2,6
R
Pullup
Pullup Resistance
(V
(V
OH
= 0.75 * V
TTD
)
N/A
50
Ω
I
Leak+
High impedance state leakage to
V
TTD
(V
leak
= V
OL
)
N/A
50
µA
3
I
Leak-
High impedance leakage to GND
(V
(V
leak
= V
OH
)
N/A
25
µA
3
C
Bus
Bus capacitance per node
N/A
10
pF
4,5
V
Noise
Signal noise immunity above
300 MHz
0.100 * V
TTD
N/A
V
p-p