Intel Xeon E7330 LF80565QH0566M Data Sheet
Product codes
LF80565QH0566M
Document Number: 318080-002
109
Thermal Specifications
shows how the PECI address is assigned to each of the processors based on
the ClusterID[1:0] and AgentID[1] setting at power on.
The Intel® 7300 Chipset chipset assigns Agent ID, Cluster ID as listed below. When the
Intel
Intel
®
Xeon
®
Processor 7200 Series and 7300 Series is used in conjunction with the
Intel® 7300 Chipset, the following PECI device addresses are generated as shown
below:
below:
FSB0 {Cluster ID[1:0], Agent ID[1]} = 000; PECI address 0x30
FSB1 {Cluster ID[1:0], Agent ID[1]} = 010; PECI address 0x32
FSB2 {Cluster ID[1:0], Agent ID[1]} = 100; PECI address 0x31
FSB3 {Cluster ID[1:0], Agent ID[1]} = 110; PECI address 0x33
The power-on-configuration (POC) settings of third-party chipsets may produce
different PECI addresses than those shown above. Thermal designers should consult
their third party chipset designers for the correct PECI addresses.
different PECI addresses than those shown above. Thermal designers should consult
their third party chipset designers for the correct PECI addresses.
Please note that each address also supports two domains (Domain 0 and Domain 1).
6.3.2.2
PECI Fault Handling Requirements
PECI is largely a fault tolerant interface, including noise immunity and error checking
improvements over other comparable industry standard interfaces. The PECI client is
as reliable as the device that it is embedded in, and thus given operating conditions
that fall under the specification, the PECI will always respond to requests and the
protocol itself can be relied upon to detect any transmission failures. There are,
however, certain scenarios where the PECI is known to be unresponsive.
improvements over other comparable industry standard interfaces. The PECI client is
as reliable as the device that it is embedded in, and thus given operating conditions
that fall under the specification, the PECI will always respond to requests and the
protocol itself can be relied upon to detect any transmission failures. There are,
however, certain scenarios where the PECI is known to be unresponsive.
Table 6-9.
BREQ# signal assertion during power on
BREQ0#
BREQ1#
AgentID[1:0] Die 0
AgentID[1:0] Die 1
Asserted
Not asserted
00
01
Asserted
Asserted
10
11
Not asserted
Asserted
This combination is not supported by the processor
Not asserted
Not asserted
Table 6-10. PECI Address assigned to processor
Cluster ID[1] / APIC
ID[4]
ClusterID[0] /
APIC ID[3]
AgentID[1] / APIC
ID[2]
PECI Address
0
0
0
0x30
0
0
1
0x31
0
1
0
0x32
0
1
1
0x33
1
0
0
0x31
1
0
1
0x30
1
1
0
0x33
1
1
1
0x32