Intel Xeon E7330 LF80565QH0566M Data Sheet
Product codes
LF80565QH0566M
Electrical Specifications
54
Document Number: 318080-002
Notes:
1.
Ta = T40 (FERR# Valid Delay from STPCLK# Deassertion).
2.
FERR# / PBE# is undefined from STPCLK# assertion until the Stop-Grant acknowledge is driven on the
FSB. FERR# / PBE# is also undefined for a period of Ta from STPCLK# deassertion. Inside these undefined
regions, the PBE# signal is driven. FERR# is driven at all other times.
Figure 2-25. FERR#/PBE# Valid Delay Timing
BCLK
STPCLK#
System bus
FERR#/PBE#
SG
Ack
FERR#
undefined
FERR#
Ta
PBE#
undefined
Figure 2-26. VID Step Timings
VID
n
n-1
m+1
m
...
Ta
Tb
Tc
Td
Ta = T84: VID Down to Valid V
CC
(max)
Tb = T82: VID Down to Valid V
CC
(min)
Tc = T85: VID Up to Valid V
CC
(max)
Td = T83: VID Up to Valid V
CC
(min)
V
CC
(max)
V
CC
(min)