Intel Celeron 1.8MHz RK80531RC033128 Data Sheet

21

All RESERVED pins must remain unconnected. Connection of these pins to V

CCCORE

, V

SS

, or to 

any other signal (including each other) can result in component malfunction or incompatibility 
with future Celeron processor products. See 

 for a pin listing of the processor and the 

location of each RESERVED pin.

For Intel Celeron processors in the S.E.P. Package, the TESTHI pin must be at a logic-high level 
when the core power supply comes up. For more information, please refer to erratum C26 of the 
Intel

®

 Processor Specification Update (Order Number 243748). Also note that the 

TESTHI signal is not available on Intel Celeron processors in the PGA package.

PICCLK must be driven with a valid clock input and the PICD[1:0] lines must be pulled-up to 
2.5 V even when the APIC will not be used. A separate pull-up resistor must be provided for each 
PICD line.

For reliable operation, always connect unused inputs or bi-directional signals to their deasserted 
signal level. The pull-up or pull-down resistor value is system dependent and should be chosen 
such that the logic-high (V

IH

) and logic-low (V

IL

) requirements are met.

For the S.E.P. Package, unused AGTL+ inputs should not be connected as the package substrate has 
termination resistors. On the other hand, the PGA packages do not have AGTL+ termination in 
their package and must have any unused AGTL+ inputs terminated through a pull-up resistor. For 
designs that intend to only support the FC-PGA/FC-PGA2 processors, unused AGTL+ inputs will 
be terminated by the processor’s on-die termination resistors and, thus, do not need to be 
terminated on the motherboard. However, the reset pin should always be terminated on the 
motherboard.

For unused CMOS inputs, active-low signals should be connected through a pull-up resistor to 
meet V

IH

 requirements and active-high signals should be connected through a pull-down resistor to 

meet V

IL

 requirements. Unused CMOS outputs can be left unconnected. A resistor must be used 

when tying bi-directional signals to power or ground. For any signal pulled to either power or 
ground, a resistor will allow for system testability.

To simplify the following discussion, the Celeron processor system bus signals have been 
combined into groups by buffer type. All Celeron processor system bus outputs are open drain 
and require a high-level source provided externally by the termination or pull-up resistor.

AGTL+ input signals have differential input buffers, which use V

REF

 as a reference signal. AGTL+ 

output signals require termination to 1.5 V. In this document, the term "AGTL+ Input" refers to the 
AGTL+ input group as well as the AGTL+ I/O group when receiving. Similarly, "AGTL+ Output" 
refers to the AGTL+ output group as well as the AGTL+ I/O group when driving.

EMI pins (S.E.P. Package only) should be connected to motherboard ground and/or to chassis 
ground through zero ohm (0 

Ω

) resistors. The zero ohm resistors should be placed in close 

proximity to the SC242 connector. The path to chassis ground should be short in length and have a 
low impedance. 

The PWRGOOD, BCLK, and PICCLK inputs can each be driven from ground to 2.5 V. Other 
CMOS inputs (A20M#, IGNNE#, INIT#, LINT0/INTR, LINT1/NMI, PREQ#, SMI, SLP#, and 
STPCLK#) must be pulled up to V

CCCMOS

. In addition, the CMOS, APIC, and TAP outputs are