Intel Celeron 1.8MHz RK80531RC033128 Data Sheet
Product codes
RK80531RC033128
Datasheet
35
Intel
®
Celeron
®
Processor up to 1.10 GHz
NOTES:
1. Unless otherwise noted, all specifications in this table apply to all Celeron processor frequencies.
2. All AC timings for the AGTL+ signals are referenced to the BCLK rising edge at 0.70 V at the processor edge
2. All AC timings for the AGTL+ signals are referenced to the BCLK rising edge at 0.70 V at the processor edge
fingers. This reference is to account for trace length and capacitance on the processor substrate, allowing the
processor core to receive the signal with a reference at 1.25 V. All AGTL+ signal timings (address bus, data
bus, etc.) are referenced at 1.00 V at the processor edge fingers.
processor core to receive the signal with a reference at 1.25 V. All AGTL+ signal timings (address bus, data
bus, etc.) are referenced at 1.00 V at the processor edge fingers.
3. All AC timings for the CMOS signals are referenced to the BCLK rising edge at 0.70 V at the processor edge
fingers. This reference is to account for trace length and capacitance on the processor substrate, allowing the
processor core to receive the signal with a reference at 1.25 V. All CMOS signal timings (compatibility
signals, etc.) are referenced at 1.25 V at the processor edge fingers.
processor core to receive the signal with a reference at 1.25 V. All CMOS signal timings (compatibility
signals, etc.) are referenced at 1.25 V at the processor edge fingers.
4. The internal core clock frequency is derived from the Intel Celeron processor system bus clock. The system
bus clock to core clock ratio is determined during initialization.
processor.
5. The BCLK period allows a +0.5 ns tolerance for clock driver variation.
6. This specification applies to Intel Celeron processors when operating at a system bus frequency of 66 MHz.
7. The BCLK offset time is the absolute difference needed between the BCLK signal arriving at the Intel Celeron
6. This specification applies to Intel Celeron processors when operating at a system bus frequency of 66 MHz.
7. The BCLK offset time is the absolute difference needed between the BCLK signal arriving at the Intel Celeron
processor edge finger at 0.5 V vs. arriving at the core logic at 1.25 V. The positive offset is needed to account
for the delay between the SC242 connector and processor core. The positive offset ensures both the
processor core and the core logic receive the BCLK edge concurrently.
for the delay between the SC242 connector and processor core. The positive offset ensures both the
processor core and the core logic receive the BCLK edge concurrently.
8. See
for Intel Celeron processor system bus clock signal quality specifications.
9. Not 100% tested. Specified by design characterization as a clock driver requirement.
Table 9. System Bus AC Specifications (Clock) at the Processor Edge Fingers
(for S.E.P. Package)
T# Parameter
Min
Nom
Max
Unit
Figure
Notes
System Bus Frequency
66.67
MHz
T1’: BCLK Period
15.0
ns
4, 5, 6
T1B’: SC242 to Core Logic BCLK Offset
0.78
ns
Absolute Value
7,8
T2’: BCLK Period Stability
± 300
ps
See
T3’: BCLK High Time
4.44
ns
@>2.0 V
6
T4’: BCLK Low Time
4.44
ns
@<0.5 V
6
T5’: BCLK Rise Time
0.84
2.31
ns
(0.5 V–2.0 V)
6, 9
T6’: BCLK Fall Time
0.84
2.31
ns
(2.0 V–0.5 V)
6, 9