Intel E3300 AT80571RG0601ML Data Sheet

30

Datasheet

1.

Unless otherwise noted, all specifications in this table apply to all processor core frequencies

based on a 200 MHz BCLK[1:0].

BCLK[1:0] Frequency

198.980

—

200.020

MHz

-

2

2.

Duty Cycle (High time/Period) must be between 40 and 60%.

T1: BCLK[1:0] Period

4.99950

—

5.00050

ns

3

3.

The period specified here is the average period. A given period may vary from this specification

as governed by the period stability specification (T2). Min period specification is based on -

300 PPM deviation from a 5 ns period. Max period specification is based on the summation of

+300 PPM deviation from a 5 ns period and a +0.5% maximum variance due to spread spectrum

clocking.

T2: BCLK[1:0] Period Stability

—

—

150

ps

4

4.

In this context, period stability is defined as the worst case timing difference between successive

crossover voltages. In other words, the largest absolute difference between adjacent clock

periods must be less than the period stability.

T5: BCLK[1:0] Rise and Fall Slew Rate

2.5

—

8

V/nS

5

5.

Measurement taken from differential waveform.

T6: Slew Rate Matching

N/A

N/A

20

%

6

6.

Matching applies to rising edge rate for Clock and falling edge rate for Clock#. It is measured

using a ±75 mV window centered on the average cross point where Clock rising meets Clock#

falling. The median cross point is used to calculate the voltage thresholds the oscilloscope is to

use for the edge rate calculations. Slew rate matching is a single ended measurement.

Threshold

Region

VH

VL

Overshoot

Undershoot

Ringback

Margin

 Rising Edge

Ringback

 Falling Edge

Ringback

BCLK0

BCLK1

Tph

Tpl

Tp

Tp  = T1: BCLK[1:0] period
T2: BCLK[1:0] period stability (not shown)
Tph = T3: BCLK[1:0] pulse high time
Tpl = T4: BCLK[1:0] pulse low time
T5: BCLK[1:0] rise time through the threshold region
T6: BCLK[1:0] fall time through the threshold region

V

CROSS (ABS

)

V

CROSS (ABS

)