Intel Core™ i7-860 Processor (8M Cache, 2.80 GHz) BX8060517860 User Manual

Datasheet

95

This register controls the closed loop thermal response of the DRAM thermal throttle 
logic. It supports immediate thermal throttle and 2X refresh. In addition, the register is 
used to configure the throttling duty cycle.

Compared against bits [36:29] of virtual temperature of each rank stored in 
RANK_VIRTUAL_TEMP to determine the throttle point. Recommended value for each 
rank is 255.

When there are more than 4 ranks attached to the channel, the thermal throttle logic is 
shared. 

17:8

RW

64

MIN_THROTTLE_DUTY_CYC. 
This parameter represents the minimum number of DCLKs of operation allowed 

after throttling. In order to provide actual command opportunities, the number 

of clocks between CKE de-assertion and first command should be considered.

4

RW

0

REF_2X_NOW. 
Direct control of dynamic 2X refresh if 

MC_THERMAL_CONTROL.THROTTLE_MODE = 2.

3:0

RW

0

THROTTLE_NOW. 
Throttler Vector to directly control throttling if 

MC_THERMAL_CONTROL.THROTTLE_MODE = 2.

31:24

RW

0

RANK3. Rank 3 throttle offset.

23:16

RW

0

RANK2. Rank 2 throttle offset.

15:8

RW

0

RANK1. Rank 1 throttle offset.

7:0

RW

0

RANK0. Rank 0 throttle offset.