Intel 2 Duo E7300 AT80571PH0673M Data Sheet

16

Datasheet

All RESERVED lands must remain unconnected. Connection of these lands to V

CC

, V

SS

, 

V

TT,

 or to any other signal (including each other) can result in component malfunction 

or incompatibility with future processors. See 

 for a land listing of the 

processor and the location of all RESERVED lands.

In a system level design, on-die termination has been included by the processor to 

allow signals to be terminated within the processor silicon. Most unused GTL+ inputs 

should be left as no connects as GTL+ termination is provided on the processor silicon. 

However, see 

 for details on GTL+ signals that do not include on-die termination.

Unused active high inputs, should be connected through a resistor to ground (V

SS

). 

Unused outputs can be left unconnected, however this may interfere with some TAP 

functions, complicate debug probing, and prevent boundary scan testing. A resistor 

must be used when tying bidirectional signals to power or ground. When tying any 

signal to power or ground, a resistor will also allow for system testability. Resistor 

values should be within ± 20% of the impedance of the motherboard trace for front 

side bus signals. For unused GTL+ input or I/O signals, use pull-up resistors of the 

same value as the on-die termination resistors (R

TT

). For details see 

.

TAP and CMOS signals do not include on-die termination. Inputs and utilized outputs 

must be terminated on the motherboard. Unused outputs may be terminated on the 

motherboard or left unconnected. Note that leaving unused outputs unterminated may 

interfere with some TAP functions, complicate debug probing, and prevent boundary 

scan testing. 

All TESTHI[12,10:0] lands should be individually connected to V

TT

 using a pull-up 

resistor which matches the nominal trace impedance.

The TESTHI signals may use individual pull-up resistors or be grouped together as 

detailed below. A matched resistor must be used for each group:

• TESTHI[1:0]
• TESTHI[7:2]
• TESTHI8/FC42 – cannot be grouped with other TESTHI signals
• TESTHI9/FC43 – cannot be grouped with other TESTHI signals
• TESTHI10 – cannot be grouped with other TESTHI signals
• TESTHI12/FC44 – cannot be grouped with other TESTHI signals

Terminating multiple TESTHI pins together with a single pull-up resistor is not 

recommended for designs supporting boundary scan for proper Boundary Scan testing 

of the TESTHI signals. For optimum noise margin, all pull-up resistor values used for 

TESTHI[12,10:0] lands should have a resistance value within ± 20% of the impedance 

of the board transmission line traces. For example, if the nominal trace impedance is 

50

Ω

, then a value between 40 Ω and 60 Ω should be used.

Power Segment Identifier (PSID) is a mechanism to prevent booting under mismatched 

power requirement situations. The PSID mechanism enables BIOS to detect if the 

processor in use requires more power than the platform voltage regulator (VR) is 

capable of supplying. For example, a 130 W TDP processor installed in a board with a 

65 W or 95 W TDP capable VR may draw too much power and cause a potential VR 

issue.