Intel 2 Duo E7300 AT80571PH0673M Data Sheet

32

Datasheet

The BSEL[2:0] signals are used to select the frequency of the processor input clock 

 defines the possible combinations of the signals and the 

frequency associated with each combination. The required frequency is determined by 

the processor, chipset, and clock synthesizer. All agents must operate at the same 

frequency. 

The Intel

®

 Core™2 Duo processor E7000 series operates at a 1333 MHz FSB and 

1066 MHz FSB frequency (selected by a 333 MHz BCLK[1:0] or 266 MHz BCLK[1:0] 

frequency). The Intel

®

 Core™2 Duo processor E8000 series operates at a 1333 MHz 

FSB frequency (selected by a 333 MHz BCLK[1:0] frequency). Individual processors will 

only operate at their specified FSB frequency.

For more information about these signals, refer to 

An on-die PLL filter solution will be implemented on the processor. The VCCPLL input is 

used for the PLL. Refer to 

 for DC specifications. 

NOTES:
1.

Unless otherwise noted, all specifications in this table apply to all processor frequencies.

2.

Crossing voltage is defined as the instantaneous voltage value when the rising edge of 
BCLK0 equals the falling edge of BCLK1. 

3.

“Steady state” voltage, not including overshoot or undershoot.

L

L

L

266 MHz

L

L

H

Reserved

L

H

H

Reserved

L

H

L

Reserved

H

H

L

Reserved

H

H

H

Reserved

H

L

H

Reserved

H

L

L

333 MHz

V

L

Input Low Voltage

-0.30

N/A

N/A

V

V

H

Input High Voltage

N/A

N/A

1.15

V

V

CROSS(abs)

Absolute Crossing Point

0.300

N/A

0.550

V

2

 ΔV

CROSS

Range of Crossing Points

N/A

N/A

0.140

V

-

V

OS

Overshoot

N/A

N/A

1.4

V

3

V

US

Undershoot

-0.300 N/A

N/A

V

3

V

SWING

Differential Output Swing

0.300

N/A

N/A

V

4