Intel 2 Duo E7300 AT80571PH0673M Data Sheet

75

Datasheet

VID[7:0]

Output

The VID (Voltage ID) signals are used to support automatic 
selection of power supply voltages (V

CC

). Refer to the Voltage 

Regulator Design Guide for more information. The voltage supply 
for these signals must be valid before the VR can supply V

CC

 to the 

processor. Conversely, the VR output must be disabled until the 
voltage supply for the VID signals becomes valid. The VID signals 
are needed to support the processor voltage specification 
variations. See 

 for definitions of these signals. The VR must 

supply the voltage that is requested by the signals, or disable itself.

VID_SELECT

Output

This land is tied high on the processor package and is used by the 
VR to choose the proper VID table. Refer to the Voltage Regulator 
Design Guide for more information.

VRDSEL

Input

This input should be left as a no connect in order for the processor 
to boot. The processor will not boot on legacy platforms where this 
land is connected to V

SS

. 

VSS

Input

VSS are the ground pins for the processor and should be connected 
to the system ground plane. 

VSSA

Input

VSSA provides isolated ground for internal PLLs on previous 
generation processors. It may be left as a No-Connect on boards 
supporting the processor. 

VSS_SENSE

Output

VSS_SENSE is an isolated low impedance connection to processor 
core V

SS

. It can be used to sense or measure ground near the 

silicon with little noise.

VSS_MB_
REGULATION

Output

This land is provided as a voltage regulator feedback sense point 
for V

SS

. It is connected internally in the processor package to the 

sense point land V27 as described in the Voltage Regulator Design 
Guide.

VTT

Miscellaneous voltage supply.

VTT_OUT_LEFT

VTT_OUT_RIGHT

Output

The VTT_OUT_LEFT and VTT_OUT_RIGHT signals are included to 
provide a voltage supply for some signals that require termination 
to V

TT

 on the motherboard. 

VTT_SEL

Output

The VTT_SEL signal is used to select the correct V

TT

 voltage level 

for the processor. This land is connected internally in the package 
to V

SS

.