Intel Xeon X3460 BX80605X3460 User Manual
Product codes
BX80605X3460
Intel® Xeon® Processor 3400 Series Datasheet, Volume 2
179
Processor Uncore Configuration Registers
4
Processor Uncore Configuration
Registers
The processor supports PCI configuration space accesses using the mechanism denoted
as Configuration Mechanism in the PCI specification as defined in the latest revision of
the PCI Local Bus Specification, as well as the PCI Express* enhanced configuration
mechanism as specified in the latest revision of the PCI Express Base Specification. All
the registers are organized by bus, device, function, and so forth, as defined in the PCI
Express Base Specification. All processor registers appear on the PCI bus assigned for
the processor socket. Bus number is derived by the max bus range setting and
processor socket number. All multi-byte numeric fields use “little-endian” ordering (that
is, lower addresses contain the least significant parts of the field).
as Configuration Mechanism in the PCI specification as defined in the latest revision of
the PCI Local Bus Specification, as well as the PCI Express* enhanced configuration
mechanism as specified in the latest revision of the PCI Express Base Specification. All
the registers are organized by bus, device, function, and so forth, as defined in the PCI
Express Base Specification. All processor registers appear on the PCI bus assigned for
the processor socket. Bus number is derived by the max bus range setting and
processor socket number. All multi-byte numeric fields use “little-endian” ordering (that
is, lower addresses contain the least significant parts of the field).
4.1
Processor Uncore Configuration Structure (PCI
Bus — FFh)
The processor Uncore contains the following PCI devices within a single, physical
component. The configuration registers for these devices are mapped as devices
residing on the PCI bus assigned for the processor socket. Bus number is derived by
the max bus range setting and processor socket number.
component. The configuration registers for these devices are mapped as devices
residing on the PCI bus assigned for the processor socket. Bus number is derived by
the max bus range setting and processor socket number.
• Device 0 — Generic processor non-core. Device 0, Function 0 contains the generic
non-core configuration registers for the processor and resides at DID (Device ID) of
2C50-7h. Device 0, Function 1 contains the System Address Decode registers and
resides at DID of 2C81h.
2C50-7h. Device 0, Function 1 contains the System Address Decode registers and
resides at DID of 2C81h.
• Device 2 — Intel QuickPath Interconnect. Device 2, Function 0 contains the
Intel QuickPath Interconnect configuration registers for Intel QuickPath
Interconnect Link 0 and resides at DID of 2C90h. Device 2, Function 1 contains the
frequency control layer registers for Intel QuickPath Interconnect Link 0 and
resides at DID of 2C91h.
Interconnect Link 0 and resides at DID of 2C90h. Device 2, Function 1 contains the
frequency control layer registers for Intel QuickPath Interconnect Link 0 and
resides at DID of 2C91h.
• Device 3 — Integrated Memory Controller. Device 3, Function 0 contains the
general registers for the Integrated Memory Controller and resides at DID of
2C98h. Device 3, Function 1 contains the Target Address Decode registers for the
Integrated Memory Controller and resides at DID of 2C99h. Device 3, Function 4
contains the test registers for the Integrated Memory Controller and resides at DID
of 2C9Ch.
2C98h. Device 3, Function 1 contains the Target Address Decode registers for the
Integrated Memory Controller and resides at DID of 2C99h. Device 3, Function 4
contains the test registers for the Integrated Memory Controller and resides at DID
of 2C9Ch.
• Device 4 — Integrated Memory Controller Channel 0. Device 4, Function 0
contains the control registers for Integrated Memory Controller Channel 0 and
resides at DID of 2CA0h. Device 4, Function 1 contains the address registers for
Integrated Memory Controller Channel 0 and resides at DID of 2CA1h. Device 4,
Function 2 contains the rank registers for Integrated Memory Controller Channel 0
and resides at DID of 2CA2h. Device 4, Function 3 contains the thermal control
registers for Integrated Memory Controller Channel 0 and resides at DID of 2CA3h.
resides at DID of 2CA0h. Device 4, Function 1 contains the address registers for
Integrated Memory Controller Channel 0 and resides at DID of 2CA1h. Device 4,
Function 2 contains the rank registers for Integrated Memory Controller Channel 0
and resides at DID of 2CA2h. Device 4, Function 3 contains the thermal control
registers for Integrated Memory Controller Channel 0 and resides at DID of 2CA3h.
• Device 5 — Integrated Memory Controller Channel 1. Device 5, Function 0
contains the control registers for Integrated Memory Controller Channel 1 and
resides at DID of 2CA8h. Device 5, Function 1 contains the address registers for
Integrated Memory Controller Channel 1 and resides at DID of 2CA9h. Device 5,
Function 2 contains the rank registers for Integrated Memory Controller Channel 1
resides at DID of 2CA8h. Device 5, Function 1 contains the address registers for
Integrated Memory Controller Channel 1 and resides at DID of 2CA9h. Device 5,
Function 2 contains the rank registers for Integrated Memory Controller Channel 1