Intel Xeon X3460 BX80605X3460 User Manual

Intel® Xeon® Processor 3400 Series Datasheet, Volume 2

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7

RO

0

IDSELWCC: IDSEL Stepping/Wait Cycle Control
Per the PCI 2.3 specification, this bit is hardwired to 0. Writes to this bit position have 

no effect.

6

RO

0

PERRE: Parity Error Response Enable
Parity error is not implemented in this host bridge. This bit is hardwired to 0. Writes 

to this bit position have no effect.

5

RO

0

VGAPSE: VGA palette snoop Enable 
This host bridge does not implement this bit. This bit is hardwired to a 0. Writes to 

this bit position have no effect.

4

RO

0

MWIEN: Memory Write and Invalidate Enable 
This host bridge will never issue memory write and invalidate commands. This bit is 

therefore hardwired to “0”. Writers to this bit position will have no effect.

3

RO

0

SCE: Special Cycle Enable
This host bridge does not implement this bit. This bit is hardwired to a 0. Writers to 

this bit position will have no effect.

2

RO

1

BME: Bus Master Enable
This host bridge is always enabled as a master. This bit is hardwired to a 1. Writes to 

this bit position have no effect.

1

RO

1

MSE: Memory Space Enable
This host bridge always allows access to main memory. This bit is not implemented 

and is hardwired to 1. Writes to this bit position have no effect.

0

RO

0

IOAE: Access Enable
This bit is not implemented in this host bridge and is hardwired to 0. Writes to this bit 

position have no effect.