Intel Xeon X3460 BX80605X3460 User Manual
Product codes
BX80605X3460
Intel® Xeon® Processor 3400 Series Datasheet, Volume 2
213
Processor Uncore Configuration Registers
4.6
Intel
QuickPath Interconnect Link Registers
4.6.1
QPI_QPILCL_L0
Intel QuickPath Interconnect Link Control.
Device:
2
Function: 0
Offset:
48h
Access as a DWord
Bit
Type
Default
Description
31:22
RO
0
Reserved
21
RW
0
L1_MASTER
Indicates that this end of the link is the L1 master. This link transmitter bit is an
Indicates that this end of the link is the L1 master. This link transmitter bit is an
L1 power state master and can initiate an L1 power state transition. If this bit is
not set, then the link transmitter is an L1 power state slave and should respond
to L1 transitions with an ACK or NACK.
If the link power state of L1 is enabled, then there is one master and one slave
If the link power state of L1 is enabled, then there is one master and one slave
per link. The master may only issue single L1 requests, while the slave can only
issue single L1_Ack or L1_NAck responses for the corresponding request.This
link transmitter bit is an L1 power state master and can initiate an L1 power
state transition. If this bit is not set, then the link transmitter is an L1 power
state slave and should respond to L1 transitions with an ACK or NACK.
If the link power state of L1 is enabled, then there is one master and one slave
If the link power state of L1 is enabled, then there is one master and one slave
per link. The master may only issue single L1 requests, while the slave can only
issue single L1_Ack or L1_NAck responses for the corresponding request.
20
RW
0
L1_ENABLE
Enables L1 mode at the transmitter. This bit should be ANDed with the receive
Enables L1 mode at the transmitter. This bit should be ANDed with the receive
L1 capability bit received during parameter exchange to determine if a
transmitter is allowed to enter into L1. This is NOT a bit that determines the
capability of a device. at the transmitter. This bit should be ANDed with the
receive L1 capability bit received during parameter exchange to determine if a
transmitter is allowed to enter into L1. This is NOT a bit that determines the
capability of a device.
19
RO
0
Reserved
18
RW
0
L0S_ENABLE
Enables L0s mode at the transmitter. This bit should be ANDed with the receive
Enables L0s mode at the transmitter. This bit should be ANDed with the receive
L0s capability bit received during parameter exchange to determine if a
transmitter is allowed to enter into L0s. This is NOT a bit that determines the
capability of a device. at the transmitter. This bit should be ANDed with the
receive L0s capability bit received during parameter exchange to determine if a
transmitter is allowed to enter into L0s. This is NOT a bit that determines the
capability of a device.
17
RWST
0
STALL_RDY_FOR_NORMAL
Link Layer Initialization stall (on next initialization) — Sticky.
0 = Disable
1 = Enable, stall initialization until this bit is cleared.
Link Layer Initialization stall (on next initialization) — Sticky.
0 = Disable
1 = Enable, stall initialization until this bit is cleared.
16
RWST
0
STALL_RDY_FOR_INIT
Link Layer Initialization stall (on next initialization) — Sticky.
0 = Disable
1 = Enable, stall initialization until this bit is cleared.
Link Layer Initialization stall (on next initialization) — Sticky.
0 = Disable
1 = Enable, stall initialization until this bit is cleared.
15:8
RO
0
Reserved
7:6
RWST
0
LLR_TIMEOUT
Link Level Retry (LLR) timeout value in flit cycles — Sticky, Late action.
00 = 4095
01 = 1023
10 = 255
11 = 63.
Link Level Retry (LLR) timeout value in flit cycles — Sticky, Late action.
00 = 4095
01 = 1023
10 = 255
11 = 63.