Intel Xeon X3460 BX80605X3460 User Manual
Product codes
BX80605X3460
Intel® Xeon® Processor 3400 Series Datasheet, Volume 2
225
Processor Uncore Configuration Registers
There are four scan chains (1 for each channel and 1 global).
Each chain is broken into smaller “sections”. Each section is composed of N bits where
N ≤ 32. Each section is used to read/write a particular parameter. Each section contains
N ≤ 32. Each section is used to read/write a particular parameter. Each section contains
N – 2 data bits (that is, the parameter to be read/written). Each section has two
additional bits: a Mask bit, and a Halt bit.
additional bits: a Mask bit, and a Halt bit.
Write Leveling Training
Yes
Yes
Yes
CS-ODT Timing & Control
Yes
No
No
Timing Delays for CMD Pins
Yes
No
No
Rank Clock Disable
Yes
Yes
No
Clock Delay
Yes
Yes
No
Transmitter Equalization Control
Yes
No
No
CKE Delay
Yes
Yes
No
Clock Slew Rate Control
No
No
No
Data Buffer Pull-up Impedance
No
No
No
IO Training Max Jitter Control
No
No
No
IO Training Number of Samples
No
No
No
Scramble Control
No
No
No
OTD compensation Control
No
No
No
DQ Driver Compensation Control
No
No
No
Table 4-18. Padscan Accessible Parameters (Sheet 2 of 2)
Parameters Accessible
Per channel
Per Rank
Per Strobe (4 pin) Group
Table 4-19. Scan Chains
Scan Chain
Chain Length
(Subject to Change)
Channel 0
5261 bits
Channel 1
5261 bits
Global chain
539 bits