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Intel Xeon X3460 BX80605X3460 User Manual

Product codes
BX80605X3460
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Processor Uncore Configuration Registers
238
Intel® Xeon® Processor 3400 Series Datasheet, Volume 2
4.10.6
MC_CHANNEL_0_REFRESH_THROTTLE_SUPPORT
MC_CHANNEL_1_REFRESH_THROTTLE_SUPPORT
This register supports Self Refresh and Thermal Throttle functions.
4.10.7
MC_CHANNEL_0_MRS_VALUE_0_1
MC_CHANNEL_1_MRS_VALUE_0_1
The initial MRS register values for MR0, and MR1 can be specified in this register. These 
values are used for the automated MRS writes used as a part of the training FSM. The 
remaining values of the MRS register must be specified here.
Device:
4, 5
Function: 0
Offset:
68h
Access as a DWord
Bit
Attr
Default
Description
31:4
RO
0
Reserved
3:2
RW
0
INC_ENTERPWRDWN_RATE 
Powerdown rate will be increased during thermal throttling based on the 
following configurations. 
00 = tRANKIDLE (Default)
01 = 16 
10 = 24 
11 = 32 
1
RW
0
DIS_OP_REFRESH 
When set the refresh engine will not issue opportunistic refresh. Setting this 
bit when either the MC_DIMM_INIT_PARAMS.QUAD_RANK_PRESENT bit or 
the MC_DIMM_INIT_PARAMS.THREE_DIMMS_PRESENT bit is set will prevent 
entry into self refresh
0
RW
0
ASR_PRESENT 
When set, this bit indicates DRAMs on this channel can support Automatic 
Self Refresh. If the DRAM is not supporting ASR (Auto Self Refresh), then 
Self Refresh entry will be delayed until the temperature is below the 2x 
refresh temperature.
Device:
4, 5
Function: 0
Offset:
70h
Access as a DWord
Bit
Attr
Default
Description
31:16
RW
0
MR1 
The values to write to MR1 for A15:A0.
15:0
RW
0
MR0 
The values to write to MR0 for A15:A0.