Intel Xeon X3460 BX80605X3460 User Manual

Intel® Xeon® Processor 3400 Series Datasheet, Volume 2

257

This register contains mask bits for MC ECC error injection. Any bits set to a 1 will flip 
the corresponding ECC bit. Correctable errors can be injected by flipping 1 bit or the 
bits within a symbol pair. Flipping bits in two symbol pairs will cause an uncorrectable 
error to be injected.

This register contains the control bits for MC ECC error injection. This register needs to 
be written after writing into MC_ECC_ERROR_MASK.

The usage model is to write the ADDR_MATCH and ERROR_MASK registers before 
writing the command in ECC_ERROR_INJECT. When writing ECC_ERROR_INJECT, the 
REPEAT_EN and CACHELINE_MASK bits need to be set to the desired values.

To turn off the feature, write 0 to the INJECT bits.

ADDRESS PARITY error injection and ECC error injection can be done either at the 
same time or independently. They will both use the same MATCH settings if both are 
enabled.

31:0

RW

0

ECCMASK. Contains the 32 bits of MC ECC mask bit for half cacheline.

31:5

RV

0

4

RW

0

INJECT_ADDR_PARITY. 
When set, this bit will force Address Parity error injection. Bit will reset after the 

first injection unless REPEAT_EN is set.

3

RW

0

INJECT_ECC. 
When set, this bit will force ECC error injection. Bit will reset after the first 

injection unless REPEAT_EN is set.

2:1

RW

0

MASK_HALF_CACHELINE.
11 = Inject the ECC code word for full cacheline.
10 = Inject the ECC code word for upper 32B half cacheline.
01 = Inject the ECC code word for lower 32B half cacheline.
00 = No masking will be applied.

0

RW

0

REPEAT_EN. 
When set, ECC errors will be injected on the channel until the bit is cleared.