Intel Xeon X3460 BX80605X3460 User Manual
Product codes
BX80605X3460
Processor Integrated I/O (IIO) Configuration Registers
28
Intel® Xeon® Processor 3400 Series Datasheet, Volume 2
3.2
Device Mapping
All devices on the Integrated I/O Module reside on PCI Bus 0.
describes the
devices and functions that the integrated I/O (IIO) module implements or routes
specifically.
specifically.
3.2.1
Unimplemented Devices/Functions and Registers
Configuration reads to unimplemented functions and devices will return all ones
emulating a master abort response. There is no asynchronous error reporting when a
configuration read master aborts. Configuration writes to unimplemented functions and
devices will return a normal response to Intel QuickPath Interconnect.
emulating a master abort response. There is no asynchronous error reporting when a
configuration read master aborts. Configuration writes to unimplemented functions and
devices will return a normal response to Intel QuickPath Interconnect.
Software should not attempt or rely on reads or writes to unimplemented registers or
register bits. Software should also not attempt to modify Reserved bits or any unused
bits called out specifically. Unimplemented registers return all zeroes when read. Writes
to unimplemented registers are ignored. For configuration writes to these registers, the
completion is returned with a normal completion status (not master-aborted).
register bits. Software should also not attempt to modify Reserved bits or any unused
bits called out specifically. Unimplemented registers return all zeroes when read. Writes
to unimplemented registers are ignored. For configuration writes to these registers, the
completion is returned with a normal completion status (not master-aborted).
3.3
PCI Express*/DMI Configuration Registers
This section covers the configuration space registers for PCI Express and DMI. The first
part of section below describes the standard PCI header space from 0h to 3Fh. The
second part describes the device specific region from 40h to FFh. The third part
describes the PCI Express enhanced configuration region.
part of section below describes the standard PCI header space from 0h to 3Fh. The
second part describes the device specific region from 40h to FFh. The third part
describes the PCI Express enhanced configuration region.
3.3.1
Other Register Notes
Note that in general, all register bits in the standard PCI header space (offset 0h–3Fh)
or in any OS-visible capability registers, that control the address decode like MSE,
IOSE, VGAEN or otherwise control transaction forwarding must be treated as dynamic
bits in the sense that these register bits could be changed by the OS when there is
traffic flowing through the IIO. Note that the address register themselves can be
or in any OS-visible capability registers, that control the address decode like MSE,
IOSE, VGAEN or otherwise control transaction forwarding must be treated as dynamic
bits in the sense that these register bits could be changed by the OS when there is
traffic flowing through the IIO. Note that the address register themselves can be
Table 3-1.
Functions Handled by the Processor Integrated I/O (IIO)
Register Group
DID
Device
Function
Comment
DMI
D130h = SRV
0
0
PCI Express Root Port 1
D138h
3
0
x16 or x8 max link width
PCI Express Root Port 2
D139h
4
0
x4 max link width. See note
PCI Express Root Port 3
D13Ah
5
0
x8 max link width
PCI Express Root Port 4
D13Bh
6
0
x4 max link width. See note
Core
D155h
8
0
Address mapping, Intel
VT-d,
System Management
Core
D156h
8
1
Semaphore and Scratchpad
registers
Core
D157h
8
2
System control/status registers
Core D158h
8
3
Miscellaneous
registers
Intel QuickPath Interconnect Port
D150h
16
0
Intel QuickPath Interconnect Link
Intel QuickPath Interconnect Port
D151h
16
1
Intel QuickPath Interconnect
Routing and Protocol