Intel Xeon X3460 BX80605X3460 User Manual
Product codes
BX80605X3460
Intel® Xeon® Processor 3400 Series Datasheet, Volume 2
35
Processor Integrated I/O (IIO) Configuration Registers
3.3.3.3
PCICMD—PCI Command Register
This register defines the PCI 3.0 compatible command register values applicable to PCI
Express space.
Express space.
Register:
PCICMD
Device:
0 (DMI)
Function: 0
Offset:
04h
Bit
Attr
Default
Description
15:11
RV
00h
Reserved
10
RW
0
Legacy Interrupt Mode Enable/Disable
9
RO
0
Fast Back-to-Back Enable
Not applicable. Hardwired to 0.
Not applicable. Hardwired to 0.
8
RW
0
SERR Enable
For PCI Express/DMI ports, this field enables notifying the internal core
For PCI Express/DMI ports, this field enables notifying the internal core
error logic of occurrence of an uncorrectable error (fatal or non-fatal) at
the port. The internal core error logic of Integrated I/O then decides if/how
to escalate the error further (pins/message, and so forth). This bit also
controls the propagation of PCI Express ERR_FATAL and ERR_NONFATAL
messages received from the port to the internal Integrated I/O core error
logic.
0 = Fatal and Non-fatal error generation and Fatal and Non-fatal error
0 = Fatal and Non-fatal error generation and Fatal and Non-fatal error
message forwarding is disabled
1 = Fatal and Non-fatal error generation and Fatal and Non-fatal error
message forwarding is enabled
Refer to the latest PCI Express Base Specification for details of how this bit
is used in conjunction with other control bits in the Root Control register
for forwarding errors detected on the PCI Express interface to the system
core error logic.
7
RO
0
IDSEL Stepping/Wait Cycle Control
Not applicable to Processor Integrated I/O devices.
Not applicable to Processor Integrated I/O devices.
Hardwired to 0.
6
RW
0
Parity Error Response
For PCI Express/DMI ports, Processor Integrated I/O ignores this bit and
For PCI Express/DMI ports, Processor Integrated I/O ignores this bit and
always does ECC/parity checking and signaling for data/address of
transactions both to and from IIO. This bit though affects the setting of Bit
8 in the PCISTS register.
5
RO
0
VGA Palette Snoop Enable
Not applicable to Processor Integrated I/O devices.
Not applicable to Processor Integrated I/O devices.
Hardwired to 0.
4
RO
0
Memory Write and Invalidate Enable
Not applicable to Processor Integrated I/O devices.
Not applicable to Processor Integrated I/O devices.
Hardwired to 0.
3
RO
0
Special Cycle Enable
Not applicable. Hardwired to 0.
Not applicable. Hardwired to 0.
2
RO
0
Bus Master Enable (BME)
For Device 0 (DMI), this bit is hardwired to 0 since the DMI is not a PCI-to-
For Device 0 (DMI), this bit is hardwired to 0 since the DMI is not a PCI-to-
PCI bridge. Hardware should ignore the functionality of this bit.
1
RO
0
Memory Space Enable (MSE)
For Device 0 (DMI), this bit is hardwired to 0 since the DMI is not a PCI-to-
For Device 0 (DMI), this bit is hardwired to 0 since the DMI is not a PCI-to-
PCI bridge.
0
RO
0
IO Space Enable (IOSE)
For Device 0 (DMI), this bit is hardwired to 0 since the DMI is not a PCI-to-
For Device 0 (DMI), this bit is hardwired to 0 since the DMI is not a PCI-to-
PCI bridge.