Intel L5618 AT80614005079AB User Manual
Product codes
AT80614005079AB
Intel
®
Xeon
®
Processor 5600 Series Datasheet Volume 1
29
Electrical Specifications
Notes:
1.
Unless otherwise specified, signals have ODT in the package with a 50 Ω pull-down to V
SS
.
2.
Unless otherwise specified, all DDR3 signals are terminated to V
DDQ
/2.
3.
DDR{0/1/2}_PAR_ERR#[2:0] are terminated to V
DDQ.
4.
TCK does not include ODT, this signal is weakly pulled-down via a 1-5 kΩ resistor to V
SS
.
5.
TDI, TMS, TRST# do not include ODT, these signals are weakly pulled-up via 1-5kΩ resistor to V
TT
.
6.
BPM[7:0]# and PREQ# signals have ODT in package with 35 Ω pull-ups to V
TT.
7.
PECI_ID# has ODT in package with a 1-5 kΩ pull-up to V
TT
.
8.
TAPPWRGOOD has ODT in package with a 1-2.5 kΩ pull-up to V
TT
.
9.
VCCPWRGOOD, VDDPWRGOOD, and VTTPWRGOOD have ODT in package with a 5-20 kΩ pull-down to V
SS
.
2.3
Mixing Processors
Intel supports dual-processor (DP) configurations consisting of processors:
• from the same power optimization segment.
• that support the same maximum Intel QuickPath Interconnect and DDR3 memory
• that support the same maximum Intel QuickPath Interconnect and DDR3 memory
speeds.
• that share symmetry across physical packages with respect to the number of
logical processor per package, number of cores per package, number of Intel
QuickPath Interconnect interfaces, and cache topology.
QuickPath Interconnect interfaces, and cache topology.
• that have identical Extended Family, Extended Model, Processor Type, Family Code
and Model Number as indicated by the Function 1 of the CPUID instruction.
Note:
Processors must operate with the same Intel QuickPath Interconnect, DDR3 memory
and core frequency.
While Intel does nothing to prevent processors from operating together, some
combinations may not be supported due to limited validation, which may result in
uncharacterized errata. Coupling this fact with the large number of Intel Xeon
processor 5600 series processor attributes, the following population rules and stepping
matrix have been developed to clearly define supported configurations.
combinations may not be supported due to limited validation, which may result in
uncharacterized errata. Coupling this fact with the large number of Intel Xeon
processor 5600 series processor attributes, the following population rules and stepping
matrix have been developed to clearly define supported configurations.
• Processors must be of the same power-optimization segment. This insures
processors include the same maximum Intel QuickPath Interconnect and DDR3
operating speeds and cache sizes.
operating speeds and cache sizes.
• Processors must operate at the same core frequency. Note, processors within the
same power-optimization segment supporting different maximum core frequencies
can be operated within a system. However, both must operate at the highest
frequency rating commonly supported. Mixing components operating at different
internal clock frequencies is not supported and will not be validated by Intel.
can be operated within a system. However, both must operate at the highest
frequency rating commonly supported. Mixing components operating at different
internal clock frequencies is not supported and will not be validated by Intel.
Table 2-6.
Signals With On-Die Termination (ODT)
Intel® QuickPath Interconnect Interface Signal Group
1
QPI[1:0]_DRX_DP[19:0], QPI[1:0]_DRX_DN[19:0], QPI[1:0]_TRX_DP[19:0], QPI[1:0]_TRX_DN[19:0],
QPI[0/1]_CLKRX_D[N/P], QPI[0/1]_CLKTX_D[N/P]
DDR3 Signal Group
1,2
DDR{0/1/2}_DQ[63:0], DDR{0/1/2}_DQS_[N/P][17:0], DDR{0/1/2}_ECC[7:0],
DDR{0/1/2}_PAR_ERR#[2:0]
3
Processor Sideband Signal Group
1
BPM#[7:0]
6
, PECI_ID#
7
, PREQ#
6,
TAPPWRGOOD
8
Test Access Port (TAP) Signal Group
TCK
4
, TDI
5
, TMS
5
, TRST#
5
Power/Other Signal Group
9
TAPPWRGOOD
8
, VCCPWRGOOD, VDDPWRGOOD, VTTPWRGOOD