Intel L5618 AT80614005079AB User Manual

40

1.

I

TT

 listed in this table is the sum of I

TTA

 and I

TTD

.

2.

This table is intended to aid in reading discrete points on 

.

3.

The V

TT_MIN

 and V

TT_MAX

 loadlines represent static and transient limits. Each is characterized by a ±31.5 mV 

offset from V

TT_TYP

.

4.

The loadlines specify voltage limits at the die measured at the VTTD_SENSE and VSS_SENSE_VTTD lands. 

Voltage regulation feedback for regulator circuits must also be taken from VTTD_SENSE and 

VSS_SENSE_VTTD lands.

1.

The V

TT_MIN

 and V

TT_MAX

 loadlines represent static and transient limits. Each is characterized by a ±31.5 mV 

offset from V

TT_TYP

.

2.

Refer to 

 for processor VTT_VID information.

3.

Refer to 

 for V

TT 

Static and Transient Tolerance.

19

VTT_VID - 0.0825

VTT_VID - 0.1140

VTT_VID - 0.1455

20

VTT_VID - 0.0885

VTT_VID - 0.1200

VTT_VID - 0.1515

21

VTT_VID - 0.0945

VTT_VID - 0.1260

VTT_VID - 0.1575

22

VTT_VID - 0.1005

VTT_VID - 0.1320

VTT_VID - 0.1635

23

VTT_VID - 0.1065

VTT_VID - 0.1380

VTT_VID - 0.1695

24

VTT_VID - 0.1125

VTT_VID - 0.1440

VTT_VID - 0.1755

25

VTT_VID - 0.1185

VTT_VID - 0.1500

VTT_VID - 0.1815

26

VTT_VID - 0.1245

VTT_VID - 0.1560

VTT_VID - 0.1875

27

VTT_VID - 0.1305

VTT_VID - 0.1620

VTT_VID - 0.1935

28

VTT_VID - 0.1365

VTT_VID - 0.1680

VTT_VID - 0.1995

-0.2125

-0.2000

-0.1875

-0.1750

-0.1625

-0.1500

-0.1375

-0.1250

-0.1125

-0.1000

-0.0875

-0.0750

-0.0625

-0.0500

-0.0375

-0.0250

-0.0125

0.0000

0.0125

0.0250

0.0375

0.0500

0

5

10

15

20

25