Intel L5618 AT80614005079AB User Manual
Product codes
AT80614005079AB
Electrical Specifications
52
Intel
®
Xeon
®
Processor 5600 Series Datasheet Volume 1
Notes:
1.
Unless otherwise noted, all specifications in this table apply to all processor frequencies.
2.
When the single ended slew rate of the input Data or Strobe signals, within a byte group, are below 1.0
V/ns, the tSU and tHD specifications must be increased by a derating factor. The input single ended slew
rate is measured DC to AC levels; V
IL
_DC to V
IH
_AC for rising edges, and V
IH
_DC to V
IL
_AC for falling
edges. Use the worse case minimum slew rate measured between Data and Strobe, within a byte group, to
determine the required derating value. No derating is required for single ended slew rates equal to or
greater than 1.0 V/ns.
3.
Edge Placement Accuracy (EPA): The silicon contains digital logic that automatically adjusts the timing
relationship
between the DDR reference clocks and DDR signals. The BIOS initiates a training procedure
that will place a given
signal appropriately within the clock period. The difference in delay between the
signal and clock is accurate to
within ±EPA. This EPA includes jitter, skew, within die variation and several
other effects.
4.
Data to Strobe read setup and Data from Strobe read hold minimum requirements specified at the
processor pad are determined with the minimum Read DQS/DQS# delay.
5.
CWL (CAS Write Latency) is the delay, in clock cycles, between the rising edge of CK where a write
command is referenced and the first rising strobe edge where the first byte of write data is present. The
CWL value is determined by the value of the CL (CAS Latency) setting.
6.
The system memory clock outputs are differential (CLK and CLK#), the CLK rising edge is referenced at the
crossing point where CLK is rising and CLK# is falling.
7.
The system memory strobe outputs are differential (DQS and DQS#), the DQS rising edge is referenced at
the crossing point where DQS is rising and DQS# is falling, and the DQS falling edge is referenced at the
crossing point where DQS is falling and DQS# is rising.
8.
This values specifies the parameter after write leveling, representing the residual error in the controller
afrter training, and does not include any effects from the DRAM itself.
T
WPRE
DQS/DQS# Write Preamble
Duration
1.425
ns
T
WPST
DQS/DQS# Write Postamble
Duration
0.825
0.674
ns
T
DQSS
CK Rising Edge Output Access
Time, Where a Write Command Is
Referenced, to the First DQS Rising
Edge
C
WL
x (T
CK
+ 4)
ns
5,6
Table 2-25. DDR3/DDR3L Electrical Characteristics and AC Specifications at 1333 MT/s
(Sheet 2 of 2)
Symbol
Parameter
Channel 0
Channel 1
Channel 2
Unit
Figure
Note
Max
Min
Table 2-26. Processor Sideband Signal Group AC Specifications (Sheet 1 of 2)
T# Parameter
Min
Max
Unit
Figure
Notes
1,2,3,4
Asynchronous GTL input pulse width
8
BCLKs
Tb: V
TT
stable to VTTPWRGOOD assertion
1
500
ms
5,7,8,10
Td: VTTPWRGOOD assertion to Dynamic V
TT
VID from
Processor
10
µs
9
Te: V
DDQ
stable to VDDPWRGOOD assertion
100
ns
5,6,7
Tf: VTTPWRGOOD to valid VID
0
10
µs
Th: V
CC
stable to VCCPWRGOOD assertion
0.05
650
ms
Ti: V
CCPLL
stable to VCCPWRGOOD assertion
1
ms
Tj: BCLK stable to VCCPWRGOOD assertion
10
BCLKs
Tk: VCCPWRGOOD assertion to RESET# de-assertion
1
10
ms
Tm: VTTPWRGOOD assertion to VCCPWRGOOD
assertion
1
ms
Tn: V
CCPLL
rise time
1.5
ms
14
Tq: PROCHOT# pulse width
500
µs
Tr:THERMTRIP# assertion until V
CC
/ V
TT
removed
500
ms