Intel BX80525KY500512 User Manual
Pentium
®
III Xeon™ Processor at 500 and 550 MHz
Datasheet
21
Most of the signals on the Pentium
III
Xeon processor system bus are in the AGTL+ signal group.
These signals are specified to be terminated to V
TT
. The DC specifications for these signals are
listed in
.
To ease connection with other devices, the Clock, CMOS, APIC, SMBus and TAP signals are
designed to interface at non-AGTL+ levels. The DC specifications for these pins are listed in
designed to interface at non-AGTL+ levels. The DC specifications for these pins are listed in
.
Note:
Unless otherwise noted, each specification applies to all Pentium
III
Xeon processors. Where
differences exist between Pentium
III
Xeon processors, look for the table entries identified by
“FMB” in order to design a Flexible Mother Board (FMB) capable of accepting all types of
Pentium
Pentium
III
Xeon processors.
Specifications are only valid while meeting specifications for case temperature, clock frequency
and input voltages. Care should be taken to read all notes associated with each parameter
and input voltages. Care should be taken to read all notes associated with each parameter
NOTES
1. Unless otherwise noted, all specifications in this table apply to all processor frequencies and cache sizes.
“FMB” is a suggested design guideline for flexible baseboard design.
2. V
CCCORE
supplies the processor core. FMB refers to the range of possible set points to expect for future
Pentium
®
III Xeon™ processors.
3. These voltages are targets only. A variable voltage source should exist on systems in the event that a
different voltage is required. See
for more information.
4. Use the Typical Voltage specification along with the Tolerance specifications to provide correct voltage
regulation to the processor.
5. V
CCL2
supplies the L2 cache. This parameter is measured at the processor edge fingers.
6. V
TT
must be held to 1.5V ±9%. It is recommended that V
TT
be held t o 1.5V ±3% while the Pentium III Xeon
processor system bus is idle. This parameter is measured at the processor edge fingers. The SC330
Table 5. Voltage Specifications
1
Symbol
Parameter
Min
Typ
Max
Unit
Notes
V
CCCORE
V
CC
for processor core FMB
All products
1.8-2.1
2.00
V
2, 3, 4
2, 3, 4
2, 3, 4
V
CCCORE
Tolerance,
Static
Static
Processor core voltage static
tolerance at edge fingers
tolerance at edge fingers
-0.085
0.085
V
7
V
CCCORE
Tolerance,
Transient
Transient
Processor core voltage transient
tolerance at edge fingers
tolerance at edge fingers
-0.130
0.130
V
7
V
CCL2
V
CC
for second level cache FMB
50 0MHz ,5 12KB
50 0MHz , 1MB
50 0MHz , 2MB
55 0MHz ,5 12KB
55 0MHz , 1MB
55 0MHz , 2MB
50 0MHz , 1MB
50 0MHz , 2MB
55 0MHz ,5 12KB
55 0MHz , 1MB
55 0MHz , 2MB
1.8-2.8
2.7
2.7
2.0
2.0
2.0
2.0
2.7
2.0
2.0
2.0
2.0
V
3, 5
3, 5
3, 5
3, 5
3, 5
3, 5
3, 5
3, 5
3, 5
3, 5
3, 5
3, 5
V
CCL2
Tolerance,
Static
Static
Static tolerance at edge fingers of
second level cache supply
second level cache supply
-0.085
0.085
V
7
V
CCL2
Tolerance,
Transient
Transient
Transient tolerance at edge fingers
of second level cache supply
of second level cache supply
-0.125
0.125
V
7
V
TT
AGTL+
bus
termination
voltage
1.365
1.50
1.635
V
6
V
CCSMB
US
SMBus supply voltage
3.135
3.3
3.465
V
3.3 V±5%
V
CCTAP
TAP supply voltage
2.375
2.50
2.625
V
2.5 V±5%