Intel BX80525KY500512 User Manual
Pentium
®
III Xeon™ Processor at 500 and 550 MHz
Datasheet
37
4.2
Low Power States and Clock Control
The Pentium
III
Xeon processor allows the use of Auto HALT, Stop-Grant, and Sleep states to
reduce power consumption by stopping the clock to specific internal sections of the processor,
depending on each particular state. There is no Deep Sleep state on the Pentium
depending on each particular state. There is no Deep Sleep state on the Pentium
III
Xeon processor.
Refer to for the following sections on low power states for the Pentium
III
Xeon processor.
For the processor to fully realize the low current consumption of the Stop Grant, and Sleep states,
an MSR bit must be set. For the MSR at 02AH (Hex), bit 26 must be set to a ‘1’ (power on default
is a ‘0’) for the processor to stop all internal clocks during these modes. For more information, see
the Intel Architecture Software Developer’s Manual, Volume III: System Programming Guide.
an MSR bit must be set. For the MSR at 02AH (Hex), bit 26 must be set to a ‘1’ (power on default
is a ‘0’) for the processor to stop all internal clocks during these modes. For more information, see
the Intel Architecture Software Developer’s Manual, Volume III: System Programming Guide.
Due to not being able to recognize bus transactions during Sleep state, SMP systems are not
allowed to have one or more processors in Sleep state and other processors in Normal or Stop Grant
states simultaneously.
allowed to have one or more processors in Sleep state and other processors in Normal or Stop Grant
states simultaneously.
4.2.1
Normal State— State 1
This is the normal operating state for the processor
4.2.2
Auto Halt Power Down State — State 2
Auto HALT is a low power state entered when the Pentium
III
Xeon processor executes the HALT
instruction. The processor will issue a normal HALT bus cycle on BE[7:0]# and REQ[4:0]# when
entering this state. The processor will transition to the Normal state upon the occurrence of SMI#,
BINIT#, INIT#, or LINT[1:0] (NMI, INTR). RESET# will cause the processor to immediately
initialize itself.
entering this state. The processor will transition to the Normal state upon the occurrence of SMI#,
BINIT#, INIT#, or LINT[1:0] (NMI, INTR). RESET# will cause the processor to immediately
initialize itself.
SMI# will cause the processor to execute the SMI handler. The return from the SMI handler can be
to either Normal Mode or the Auto HALT Power Down state. See Chapter 11 in the Intel
Architecture Software Developer’s Manual, Volume III: System Programming Guide.
to either Normal Mode or the Auto HALT Power Down state. See Chapter 11 in the Intel
Architecture Software Developer’s Manual, Volume III: System Programming Guide.
FLUSH# will be serviced during Auto HALT state. The on-chip first level caches and external
second level cache will be flushed and the processor will return to the Auto HALT state.
second level cache will be flushed and the processor will return to the Auto HALT state.
A20M# will be serviced during Auto HALT state; the processor will mask physical address bit 20
(A20#) before any look-up in either the on-chip first level caches or external second level cache,
and before a read/write transaction is driven on the bus.
(A20#) before any look-up in either the on-chip first level caches or external second level cache,
and before a read/write transaction is driven on the bus.
The system can generate a STPCLK# while the processor is in the Auto HALT Power Down state.
The processor will generate a Stop Grant bus cycle when it enters the Stop Grant state from the
HALT state. If the processor enters the Stop Grant state from the Auto HALT state, the STPCLK#
signal must be deasserted before any interrupts are serviced (see below). When the system
deasserts the STPCLK# interrupt signal, the processor will return execution to the HALT state. The
processor will not generate a new HALT bus cycle when it re-enters the HALT state from the Stop
Grant state.
The processor will generate a Stop Grant bus cycle when it enters the Stop Grant state from the
HALT state. If the processor enters the Stop Grant state from the Auto HALT state, the STPCLK#
signal must be deasserted before any interrupts are serviced (see below). When the system
deasserts the STPCLK# interrupt signal, the processor will return execution to the HALT state. The
processor will not generate a new HALT bus cycle when it re-enters the HALT state from the Stop
Grant state.