Intel BX80525KY500512 User Manual
Pentium
®
III Xeon™ Processor at 500 and 550 MHz
Datasheet
93
9.1.31
L2_SENSE
The L2_SENSE pin is connected to the VCC_L2 power plane on the substrate.
9.1.32
NMI - See LINT1
9.1.33
PICCLK (I)
The PICCLK (APIC Clock) signal is an input clock to the processor and core logic or I/O APIC
which is required for operation of all processors, core logic, and I/O APIC components on the
APIC bus. During FRC mode operation, PICCLK must be 1/4 of (and synchronous to) BCLK.
which is required for operation of all processors, core logic, and I/O APIC components on the
APIC bus. During FRC mode operation, PICCLK must be 1/4 of (and synchronous to) BCLK.
9.1.34
PICD[1:0] (I/O)
The PICD[1:0] (APIC Data) signals are used for bi-directional serial message passing on the APIC
bus, and must connect the appropriate pins of all processors and core logic or I/O APIC
components on the APIC bus.
bus, and must connect the appropriate pins of all processors and core logic or I/O APIC
components on the APIC bus.
9.1.35
PM[1:0]# (O)
The PM[1:0]# (Performance Monitor) signals are outputs from the processor which indicate the
status of programmable counters used for monitoring processor performance.
status of programmable counters used for monitoring processor performance.
9.1.36
PRDY# (O)
The PRDY (Probe Ready) signal is a processor output used by debug tools to determine processor
debug readiness. See
debug readiness. See
for more information on this signal.
9.1.37
PREQ# (I)
The PREQ# (Probe Request) signal is used by debug tools to request debug operation of the
processors. See
processors. See
for more information on this signal.
9.1.38
PWREN[1:0] (I)
These 2 pins are tied directly together on the processor. They can be used to detect processor
presence by applying a voltage to one pin and observing it at the other. See
presence by applying a voltage to one pin and observing it at the other. See
for the
maximum rating for this signal.
9.1.39
PWRGOOD (I)
The PWRGOOD (Power Good) signal is a 2. 5V tolerant processor input. The processor requires
this signal to be a clean indication that the clocks and power supplies (V
this signal to be a clean indication that the clocks and power supplies (V
CCCORE
, V
CCL2
, V
CCTAP
,
V
CCSMB
US
) are stable and within their specifications. Clean implies that the signal will remain low
(capable of sinking leakage current), without glitches, from the time that the power supplies are
turned on until they come within specification. The signal must then transition monotonically to a
high (2.5 V ) state.
turned on until they come within specification. The signal must then transition monotonically to a
high (2.5 V ) state.
illustrates the relationship of PWRGOOD to other system signals.