Intel L5630 AT80614005484AA User Manual

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Signals that include on-die termination (ODT) are listed in 

Single ended

CMOS Output

DDR{0/1/2}_CS#[7:0], DDR{0/1/2}_ODT[5:0], 

DDR{0/1/2}_CKE[3:0]

Single ended

Analog Input

DDR_VREF, DDR_COMP[2:0]

Single ended

CMOS Input/Output

DDR{0/1/2}_DQ[63:0], DDR{0/1/2}_ECC[7:0]

Differential

CMOS Input/Output

DDR{0/1/2}_DQS_[N/P][17:0]

Single ended

Asynchronous Input

DDR{0/1/2}_PAR_ERR#[2:0], 

DDR_THERM#, DDR_THERM2#

Single ended

Asynchronous Input/Output

PECI

Single ended

GTL Input/Output

BPM#[7:0], CAT_ERR#

Single ended

Asynchronous Input

PECI_ID#

Single ended

Asynchronous GTL Output

PRDY#, THERMTRIP#

Single ended

Asynchronous GTL Input

PREQ#

Single ended

Asynchronous GTL Input/Output

PROCHOT#

Single ended

Asynchronous CMOS Output

PSI#, TAPPWRGOOD

Single ended

CMOS Output

VID[7:6],
VID[5:3]/CSC[2:0],
VID[2:0]/MSID[2:0],
VTT_VID[4:2]

Single ended

Asynchronous Input

VCCPWRGOOD, VDDPWRGOOD, VTTPWRGOOD

Single ended

Reset Input

RESET#

Differential

Input

BCLK_DP, BCLK_DN

Differential

CMOS Output

BCLK_ITP_DP, BCLK_ITP_DN

Single ended

Input

TCK, TDI, TMS, TRST#

Single ended

GTL Output

TDO

Power / Ground

V

CC

, V

CCPLL

, V

DDQ

,

 

V

TTA

, V

TTD

, V

SS

Analog Input

COMP0, ISENSE

Sense Points

VCCSENSE, VSSSENSE, VSS_SENSE_VTTD, 

VTTD_SENSE

Other

SKTOCC#, DBR#

1.

Refer to 

 for land assignments and 

 for signal definitions.

2.

DDR{0/1/2} refers to DDR3 channel 0, DDR3 channel 1, and DDR3 Channel 2