Intel AT80604004872AA User Manual

Intel® Xeon® Processor 7500 Datasheet, Volume 1

153

Features

7.5.1.2

PISIZE: PIROM Size

This location identifies the PIROM size. Writes to this register have no effect.

7.5.1.3

PDA: Processor Data Address

This location provides the offset to the Processor Data Section. Writes to this register
have no effect.

7.5.1.4

PCDA: Processor Core Data Address

This location provides the offset to the Processor Core Data Section. Writes to this
register have no effect.

Offset:

00h

Bit

Description

7:0

Data Format Revision

The data format revision is used whenever fields within the PIROM are

redefined. The initial definition will begin at a value of 1. If a field, or bit

assignment within a field, is changed such that software needs to discern

between the old and new definition, then the data format revision field will be

incremented.

00h: Reserved
01h: Initial definition
02h: Second revision
03h: Third revision
04h: Fourth revision
05h:Fifth revision (Defined by this document)
06h-FFh: Reserved

Offset:

01h-02h

Bit

Description

15:0

PIROM Size

The PIROM size provides the size of the device in hex bytes. The MSB is at

location 01h; the LSB is at location 02h.

0000h - 007Fh: Reserved

0080h: 128 byte PIROM size

0081- FFFFh: Reserved

Offset:

03h

Bit

Description

7:0

Processor Data Address

Byte pointer to the Processor Data section

00h: Processor Data section not present

01h - 0Dh: Reserved

0Eh: Processor Data section pointer value

0Fh-FFh: Reserved