Intel AT80604004872AA User Manual

162

Intel® Xeon® Processor 7500 Datasheet, Volume 1

Example: The Intel® Xeon® processor 7500 series supports Intel® QPI Version 
Number 1.0. Therefore, offset 2Eh-31h has an ASCII value of “01.0”, which is 30, 31, 
2E, 30.

This location contains the LT-SX location, which is a two-bit field and is LSB aligned. A 
value of 00b indicates LT-SX is not supported. A value of 01b indicates LT-SX is 
supported. Writes to this register have no effect.

Example: A processor supporting LT-SX will have offset 32h set to 01h.

Systems may need to read this offset to decide on compatible processors and MBK1 
capabilities. The data provided is the transfer rate, rounded to a whole number, and 
reflected in binary coded decimal. Writes to this register have no effect.

Example: The Intel® Xeon® processor 7500 series supports a maximum Intel® SMI 
transfer rate of 6.4 GT/s. Therefore, offset 33h-34h has a value of 6400h.

This listing provides the minimum “operating” Intel® SMI transfer rate. Systems may 
need to read this offset to decide if processors and MBK1s support the same Intel® 
SMI Transfer Rate. The data provided is the transfer rate, rounded to a whole number, 
and reflected in binary coded decimal. Writes to this register have no effect.

31:0

00000000h-FFFFFFFFh: MHz

7:2

000000b-111111b: Reserved

1:0

LT-SX support indicator

00b: Not supported

01b: Supported

10b-11b: Reserved

15:0

0000h-FFFFh: MHz