Intel AT80604004872AA User Manual

172

Intel® Xeon® Processor 7500 Datasheet, Volume 1

Bits are set when a feature is present, and cleared when they are not.

This location contains 2 bits for representing the supported number of physical 
processors on the bus. These two bits are LSB aligned where 00b equates to single-
processor operation, 01b to scalable 2 socket (S2S), 10 to scalable 4 socket (S4S), and 
scalable 8 socket (S8S). Intel® Xeon® processor 7500 series is a S2S, S4S, or S8S 
processor. The first six bits in this field are reserved for future use. Writes to this 
register have no effect.

Example: A scalable 8 socket processor will have a value of 03h at offset 71h.

At offset 73, a 4-bit hex digit is used to tell how many devices are in the TAP Chain. 
Because the Intel® Xeon® processor 7500 series has four cores, this field would be set 
to 4h.

3

Execute  Disable

2

Intel

®

 64

1

Intel

®

 Thermal Monitor 2

0

Enhanced Intel SpeedStep

®

 Technology

7:2

000000b-111111b: Reserved

1:0

Single Socket, S2S, S4S or S8S indicator

00b: Single Socket

01b: Scalable 2 Socket

10b: Scalable 4 Socket

11b: Scalable 8 Socket

7:0

0000h-FFFFh: Reserved