Intel AT80604004872AA User Manual

Page of 172
Intel® Xeon® Processor 7500 Datasheet, Volume 1
33
Electrical Specifications
2.5.2
Intel® QPI Electrical Specifications
The applicability of this section applies to Intel® QPI within a links-based Enterprise MP 
class server platform, designated as the Intel® QPI channel. This section contains 
information for slow boot up speed (1/4 frequency of the reference clock), 4.8 GT/s, 
and 6.4 GT/s.
The transfer rates available for the Intel® Xeon® processor 7500 series are shown in 
.
2.5.2.1
Requirements at 1/4 RefClk Signaling Rate
The signaling rate is defined as 1/4 the rate of the System Reference Clock. For 
example, a 133 MHz System Reference Clock would have a forwarded clock frequency 
of 33.33 MHz and the signaling rate would be 66.66 MT/s. 
L
D+/D-RX-Skew
Phase skew between D+ 
and D- lines for any data 
bit at Rx
0.03
UI
BER
Lane
Bit Error Rate per lane 
valid for 4.8 and 6.4 GT/s
1.0E-14
Events
Voh_bscan
Output high during 
boundary scan
VIO-100
VIO
mV
Vol_bscan
Output low during 
boundary scan
0
100
mV
Vih_bcan
Input high during 
boundary scan
0.86 * VIO
V
Vil_bscan
Output low during 
boundary scan
0.40 * VIO V
Notes:
1. Return loss specifications for receiver package are not provided. However, maintaining a well impedance
matched and low loss receiver package is crucial for a successful silicon operation, including maintaining as
low as possible on-die capacitance.
2. Used during initialization. It is the state of “OFF” condition for the receiver when only the minimum termination
is connected.
Table 2-10. Link Speed Independent Specifications (Sheet 2 of 2)
Symbol
Parameter
Min
Nom
Max
Unit
Notes
Table 2-11. Clock Frequency Table 
Intel® QPI System Interface 
Forwarded Clock Frequency
Intel® QPI System Interface 
Data Transfer Rate
33.33 MHz
66.66 MT/s
1
Notes:
1. This speed is the 1/4 RefClk Frequency.
2.40 GHz
4.8 GT/s
3.20 GHz
6.4 GT/s