Intel AT80604004872AA User Manual
Intel® Xeon® Processor 7500 Datasheet, Volume 1
41
Electrical Specifications
2.5.4.2
Summary of Transmitter Output Specifications
Notes:
1.
Specified at the package pins into a timing and voltage compliance test load.
2.
The maximum value is specified to be at least (V
TX-DIFFp-p L
/ 4) + V
TX-CM L
+ (V
TX-CM-ACp-p
/ 2)
3.
Measured from the reference clock edge to the center of the output eye. This specification must be met across specified
voltage and temperature ranges for a single component. Drift rate of change is significantly below the tracking capability of
the receiver.
2.5.4.3
Intel® SMI Differential Receiver Input Specifications
The receiver definition starts from the input pin of the receiver end package and
therefore includes the package and the receiver end chip.
therefore includes the package and the receiver end chip.
2.5.4.3.1
Receiver Input Compliance Eye Specification
Following the specification of the transmitter, the receiver is specified in terms of the
minimum input eye height that must be maintained at the input to the receiver, and
under which the receiver must function at the specified data rates. In addition to eye
height, there are timing specifications that must also be met for both the data lanes
and the forwarded clock.
minimum input eye height that must be maintained at the input to the receiver, and
under which the receiver must function at the specified data rates. In addition to eye
height, there are timing specifications that must also be met for both the data lanes
and the forwarded clock.
Table 2-21. Summary of Differential Transmitter Output Specifications
Symbol
Parameter
Min
Max
Units
Comments
V
TX-CM-Ratio
Ratio of V
TX-CM
to measured
V
TX-DIFFp-p (DC)
23
27
%
V
TX-CM-AC-Ratio
Ratio of V
TX-CM-ACp-p
to
measured V
TX-DIFFp-p (DC)
7.5
%
V
TX-SE
Single-ended voltage
(w.r.t. VSS) on D+/D-
-75
750
mV
T
TX_TJ
Transmitter total jitter
0.25
T
TX_DJ
Transmitter dual-dirac
deterministic jitter
0.15
UI
T
TX_PWS
Transmitter pulse width
shrinkage (data)
0.05
T
TX_CLK_PWS
Transmitter pulse width
shrinkage (forwarded clock)
0.018
UI
ER
TX-RISE
,
ER
TX-FALL
Differential TX output edge
rates
10
30
V/ns
Differential voltage levels at +/- 100 mV
Measured as:
Measured as:
RL
TX-DIFF
Differential return loss
8
dB
Measured relative to 50 ohms over
0.1GHz to 3.2 GHz.
RL
TX-CM
Common mode return loss
6
dB
Measured relative to 50 ohms over
0.1GHz to 3.2 GHz.
R
TX
Transmitter termination
resistance
37.4
47.6
Ω
L
TX-SKEW
Lane-to-lane skew at TX
100
+ 2 UI
ps
L
TX-SKEW-CLK-DAT
TX clock-to-data skew
-0.2
0.2
ns
Forwarded clock delay - data delay
L
TOT-SKEW-CLK-DAT
Total system clock-to-data
skew
-1.5
1.5
ns
T
TX-DRIFT
Maximum TX Drift
240
ps
BER
Bit Error Ratio
10
-12