Intel AT80604004872AA User Manual
Electrical Specifications
56
Intel® Xeon® Processor 7500 Datasheet, Volume 1
Figure 2-28. Voltage Sequence Timing Requirements
VCCI
O
VCCREG
Vcache
Vcore
BCLK/BCLK_N
P
W
R
GOOD
RESET_
N
10
BC
L
KS mi
n
3
4
ms mi
n
V
IO
_
P
W
R
GOOD
CVI
D
s
VI
Ds
~
2
5
m
s m
a
x*
CVID
(VccC
a
c
h
e
set a
nd doe
s not cha
nge a
fter
re
s
e
t)
B
o
ot v
o
ltage
=1
.1
V
VID (
fused val
ues
)
PC
U
w
ill d
e
ter
m
in
e
init
ia
l
V
ID
v
a
lue
a
fter res
e
t
is
dea
ss
ert
e
d
V
C
CR
E
G
_
GOOD
=VC
A
CH
E
_
O
U
TEN
Vcache_VR
_
RDY
=VC
O
RE_OUT
EN
Vcor
e
_
VR_
R
DY
2
00
R
in
g
O
s
c clo
c
k
s
, m
a
x
~
4uS
for
50
M
H
z
VID POC
SKTDI
S
_
N
RESET st
raps
1
08 bc
lks
m
in
.
0
.05m
s
-3m
s*
V
c
ore adjus
ts
ac
co
rd
in
g
ly.
VI
Ds st
art
dri
v
in
g
at
V
c
ache
=0
.7
5
V
mi
cr
os
ec
on
d
s
0
.0
5
ms
-3
.5
ms*
B
oot voltag
e=
1.1
V
0.
0
5
ms
-3
ms*
0.
0
5
ms-
3.
5ms
*
Vio rela
ted pins m
ust n
ot be d
riven
above V
CCIO. Re
sistive p
ull-ups
need
to be tied to
VCCIO;
activ
ely d
riv
en sig
nals
must be
gated by
VIOP
WRGOOD
VI
D POC l
a
tc
h
e
d
0ms
-5ms
*
V
C
CI
O
t
o
p
o
w
e
rg
oo
d
: no
ma
x
B
O
O
T
M
O
DE[1
:0],
LT-
S
X, FLA
S
H
R
O
M
_
C
F
G
[2:0
],
S
K
T
DIS
#
, R
U
NB
IST
3.
3
V
1
SKTO
C
C_N
2
5
10
0
m
s
m
in
7
4
9
6
10
S
K
T
ID
[2
:0
]
8
2b
cl
ks se
tu
p
VR11
.0
D
G
rev 2
.0)
V
C
CI
O_
OUT
E
N