Intel 9140N NE80567KE025009 User Manual

24

VCCIO

Processor I/O supply voltage at package 

pin including all AC and DC

1.147

1.175

1.203

V

8

VCCA

Processor analog supply voltage (DC spec)

1.764

1.8

1.836

V

VCCA

Processor analog supply voltage (AC 

tolerance for noise at scope full 

bandwidth)

1.8

25

mV

9, 10

VCCA

Processor analog supply voltage (AC 

tolerance for noise > 1MHz)

1.8

15

mV

9, 11

VCCA

Processor analog supply voltage (Total = 

DC spec + AC tolerance)

1.739

1.8

1.861

V

VCC33_SM

3.3 V supply voltage

3.135

3.3

3.465

V

1. These voltages are target only. A variable voltage source should exist on systems in the event that a different voltage is required.

See 

Section 2.9

 and Ararat  170 Watt  Voltage Regulator Design Guide for more information.

2. Uncore, Core, and Cache voltage and Current Rating are at the Package Pad.

3. The voltage specification requirements are measured across the V

CCCORESENSE

 and V

SSCORESENSE

 pins using an oscilloscope set

to a 100 MHz bandwidth and probes that are 1.5 pF maximum capacitance and 1 M minimum impedance at the processor

socket. The maximum length of ground wire on the probe should be less than 5 mm. Ensure external noise from the system is

not coupled into the scope probe.

4. The voltage specification requirements are measured across the V

CCUNCORESENSE

 and V

SSUNCORESENSE

 pins using an oscilloscope

set to a 100 MHz bandwidth and probes that are 1.5 pF maximum capacitance and 1 M minimum impedance at the processor

socket. The maximum length of ground wire on the probe should be less than 5 mm. Ensure external noise from the system is

not coupled into the scope probe.

5. The voltage specification requirements are measured across the V

CCCACHESENSE

 and V

SSCACHESENSE

 pins using an oscilloscope set

to a 100 MHz bandwidth and probes that are 1.5 pF maximum capacitance and 1 M minimum impedance at the processor

socket. The maximum length of ground wire on the probe should be less than 5 mm. Ensure external noise from the system is

not coupled into the scope probe.

6. Warm boot reset, only in downward direction.

7. Min and Max range is spec at the die for both VCCIO and VCCIO_FBD. This range includes 50 mV p-p AC noise. It also includes

any DC and AC tolerances at package pin.

8. The FMB remote sense tolerance is ±2.5% for DC to 20 MHz at the package, where ±1.5% is allotted for a DC to 1 MHz range

and an additional ±1% for 1 MHz to 20 MHz. Similarly, ±6.4% is allotted for DC to 20 MHz at the die. It is expected that VCCIO

regulators meet ±1.5% at the remote sense location based on the general remote sense termination point location as described

, VR Sense Point (Representation). For future processor compatibility, it is strongly recommended that the platform

query the PIROM to assure VCCIO is set to the appropriate level prior to powering up the VCCIO supply.

9. All voltage regulation measurements taken at remote sense termination points.

10.For peak-to-peak Ripple and Noise (R&N) measured with full bandwidth (BW) of the scope (Min 1 GHz BW scope is required):

set scope diff probe and the scope at full BW (capture waveform A, channel 1).

11.For peak-to-peak Ripple and Noise (R&N) measured above 1 MHz:

 Step 1 = set both: scope diff probe and/or the scope at 1 MHz BW limit (capture waveform B, channel 2)

 Step 2 = calculate A-B (use scope Math function:   subtract channel 1 - channel 2).

I

CC_CORE

I

CC 

for core

151

A

I

CC_CORE_TDC

Thermal Design Current for Core

100

A

1

I

CC_CORE_STEP

Max Load step for core

95

A

2

dI

CC_CORE

/dt

Slew rate for core at Ararat output

154

A/us

I

CC_UNCORE

I

CC 

for uncore

50

A

I

CC_UNCORE_TDC

Thermal Design Current for Uncore

43

A

3

I

CC_UNCORE_STEP

Max Load step for uncore

22

A

4

dI

CC_UNCORE

/dt

Slew rate for uncore at Ararat output

75

A/us

I

CC_CACHE

I

CC

 for processor cache

50

A

I

CC_CACHE_TDC

Thermal Design Current for Cache

50

A

5

I

CC_CACHE_STEP

Max Load step for cache

25

A

6