Intel 2 Quad Q8400S AT80580AJ0674ML User Manual
Product codes
AT80580AJ0674ML
Datasheet
27
Electrical Specifications
NOTES:
1.
1.
Refer to
for signal descriptions.
2.
In processor systems where no debug port is implemented on the system board, these
signals are used to support a debug port interposer. In systems with the debug port
implemented on the system board, these signals are no connects.
signals are used to support a debug port interposer. In systems with the debug port
implemented on the system board, these signals are no connects.
3.
The value of these signals during the active-to-inactive edge of RESET# defines the
processor configuration options. See
processor configuration options. See
for details.
4.
PROCHOT# signal type is open drain output and CMOS input.
.
NOTES:
1.
1.
Signals that do not have R
TT
, nor are actively driven to their high-voltage level.
NOTE:
1.
1.
for more information.
GTL+ Strobes
Synchronous to
BCLK[1:0]
BCLK[1:0]
ADSTB[1:0]#, DSTBP[3:0]#, DSTBN[3:0]#
CMOS
A20M#, DPSLP#, DPRSTP#, IGNNE#, INIT#, LINT0/
INTR, LINT1/NMI, SMI#
INTR, LINT1/NMI, SMI#
3
, STPCLK#, PWRGOOD, SLP#,
TCK, TDI, TDI_M, TMS, TRST#, BSEL[2:0], VID[7:0],
PSI#
PSI#
Open Drain
Output
Output
FERR#/PBE#, IERR#, THERMTRIP#, TDO, TDO_M
Open Drain
Input/Output
Input/Output
PROCHOT#
4
FSB Clock
Clock
BCLK[1:0], ITP_CLK[1:0]
2
Power/Other
VCC, VTT, VCCA, VCCIOPLL, VCCPLL, VSS, VSSA,
GTLREF[3:0], COMP[8,3:0], RESERVED, TESTHI[10,7:0],
VCC_SENSE, VCC_MB_REGULATION, VSS_SENSE,
VSS_MB_REGULATION, DBR#
GTLREF[3:0], COMP[8,3:0], RESERVED, TESTHI[10,7:0],
VCC_SENSE, VCC_MB_REGULATION, VSS_SENSE,
VSS_MB_REGULATION, DBR#
2
, VTT_OUT_LEFT,
VTT_OUT_RIGHT, VTT_SEL, FCx, PECI, MSID[1:0]
Table 2-6.
FSB Signal Groups (Sheet 2 of 2)
Signal Group
Type
Signals
1
Table 2-7.
Signal Characteristics
Signals with R
TT
Signals with No R
TT
A[35:3]#, ADS#, ADSTB[1:0]#, BNR#, BPRI#,
D[63:0]#, DBI[3:0]#, DBSY#, DEFER#,
DRDY#, DSTBN[3:0]#, DSTBP[3:0]#, HIT#,
HITM#, LOCK#, PROCHOT#, REQ[4:0]#,
RS[2:0]#, TRDY#
D[63:0]#, DBI[3:0]#, DBSY#, DEFER#,
DRDY#, DSTBN[3:0]#, DSTBP[3:0]#, HIT#,
HITM#, LOCK#, PROCHOT#, REQ[4:0]#,
RS[2:0]#, TRDY#
A20M#, BCLK[1:0], BSEL[2:0],
COMP[8,3:0], FERR#/PBE#, IERR#, IGNNE#,
INIT#, ITP_CLK[1:0], LINT0/INTR, LINT1/
NMI, MSID[1:0], PWRGOOD, RESET#, SMI#,
STPCLK#, TDO, TDO_M, TESTHI[10,7:0],
THERMTRIP#, VID[7:0], GTLREF[3:0], TCK,
TDI, TDI_M, TMS, TRST#, VTT_SEL
COMP[8,3:0], FERR#/PBE#, IERR#, IGNNE#,
INIT#, ITP_CLK[1:0], LINT0/INTR, LINT1/
NMI, MSID[1:0], PWRGOOD, RESET#, SMI#,
STPCLK#, TDO, TDO_M, TESTHI[10,7:0],
THERMTRIP#, VID[7:0], GTLREF[3:0], TCK,
TDI, TDI_M, TMS, TRST#, VTT_SEL
Open Drain Signals
1
THERMTRIP#, FERR#/PBE#, IERR#, BPM[5:0]#,
BPMb[3:0]#, BR0#, TDO, TDO_M, FCx
BPMb[3:0]#, BR0#, TDO, TDO_M, FCx
Table 2-8.
Signal Reference Voltages
GTLREF
V
TT
/2
BPM[5:0]#, BPMb[3:0]#, RESET#, BNR#, HIT#,
HITM#, BR0#, A[35:0]#, ADS#, ADSTB[1:0]#,
BPRI#, D[63:0]#, DBI[3:0]#, DBSY#, DEFER#,
DRDY#, DSTBN[3:0]#, DSTBP[3:0]#, LOCK#,
REQ[4:0]#, RS[2:0]#, TRDY#
HITM#, BR0#, A[35:0]#, ADS#, ADSTB[1:0]#,
BPRI#, D[63:0]#, DBI[3:0]#, DBSY#, DEFER#,
DRDY#, DSTBN[3:0]#, DSTBP[3:0]#, LOCK#,
REQ[4:0]#, RS[2:0]#, TRDY#
A20M#, LINT0/INTR, LINT1/NMI, IGNNE#,
INIT#, PROCHOT#, PWRGOOD
INIT#, PROCHOT#, PWRGOOD
1
, SMI#,
STPCLK#, TCK
1
, TDI
1
, TDI_M
1
, TMS
1
,
TRST#
1