Intel Itanium 9350 LW80603002589AA User Manual

Product codes
LW80603002589AA
Page of 120
Intel
®
 Itanium
® 
Processor 9300 Series Datasheet
19
Electrical Specifications
Notes:
1.
Parameter value at 1/4 QPI Refclk
2.
Parameter value at full QPI Refclk
3.
The termination small signal resistance; tolerance over the entire signalling voltage range shall not exceed +/-5 ohms with 
regard to the average of the values measured in the high output voltage state and the low output voltage state for that pin.
4.
HVM guaranteed error free value for stressed PRBS signaling across PVT. LInk BER is the dominant spec of which eye 
dimensions are only one factor, and improving another factor could compensate for eye height or width.
5.
HVM guaranteed error free value for stressed ‘1010 signaling across PVT. Link BER is the dominant spec of which eye 
dimensions are only one factor, and improving another factor could compensate for eye height or width.
6.
See 
V
Rx-data-cm-pin
Receiver data common mode level
125
350
mV
2
V
Rx-data-cm-ripple-
pin
Receiver data common mode ripple
0
100
mV
p-p
V
Rx-clk-cm-pin
Receiver clock common mode level
175
350
mV
V
Rx-clk-cm-ripple-pin
Receiver clock common mode ripple
0
100
mV
p-p
V
RX-eye-data-pin
Minimum eye height at pin for data
200
mV
4
V
RX-eye-clk-pin
Minimum eye height at pin for clk
225
mV
5
T
RX-eye-pin
Minimum eye width at pin for clk and data
0.6
UI
4
QPI BER
Lane
Bit Error Rate per lane valid for 4.8 and 6.4 GT/s
1.0E-14
Events
SMI BER
Lane
Bit Error Rate per lane valid for 4.8 and 6.4 GT/s
1.0E-12
Events
Table 2-6.
Receiver Parameter Values for Intel QuickPath Interconnect and Intel SMI
Channels @ 4.8 GT/
Symbol
Parameter
Min
Nom
Max
Units
Notes
Figure 2-2. Single-ended Maximum and Minimum Levels and V
cross
 Levels
Figure 2-3. V
cross-delta
 Definition