Intel Xeon 7130N LF80550KF0878M Data Sheet
Product codes
LF80550KF0878M
Introduction
12
Dual-Core Intel
®
Xeon
®
Processor 7000 Series Datasheet
which are accessed through an SMBus interface and contain information relevant to the particular
processor and system in which it is installed. Thermal management and further thermal redundancy
can be achieved with the use of the Thermal Monitor feature.
processor and system in which it is installed. Thermal management and further thermal redundancy
can be achieved with the use of the Thermal Monitor feature.
The Dual-Core Intel Xeon processor 7000 series supports Intel
®
64 as an enhancement to Intel's
IA-32 architecture. This enhancement allows the processor to execute operating systems and
applications written to take advantage of the 64-bit extension technology. Further details on Intel
64 and its programming model can be found in the 64-bit Extension Technology Software
Developer's Guide at
applications written to take advantage of the 64-bit extension technology. Further details on Intel
64 and its programming model can be found in the 64-bit Extension Technology Software
Developer's Guide at
http://developer.intel.com/technology/64bitextensions/
.
The Dual-Core Intel Xeon processor 7000 series is packaged in a 604-pin Flip-Chip Micro Pin
Grid Array (FC-mPGA4) package and utilizes a surface-mount Zero Insertion Force (ZIF)
mPGA604 socket. The Dual-Core Intel Xeon processor 7000 series supports 40-bit addressing.
Grid Array (FC-mPGA4) package and utilizes a surface-mount Zero Insertion Force (ZIF)
mPGA604 socket. The Dual-Core Intel Xeon processor 7000 series supports 40-bit addressing.
The Dual-Core Intel Xeon processor 7000 series uses a scalable system bus protocol referred to as
the “front side bus” in this document. The FSB utilizes a split-transaction, deferred reply protocol.
The FSB uses Source-Synchronous Transfer (SST) of address and data to improve performance.
The processor transfers data four times per bus clock (4X data transfer rate). Along with the 4X
data bus, the address bus can deliver addresses two times per bus clock and is referred to as a
‘double-clocked’, ‘double-pumped’, or the 2X address bus. In addition, the Request Phase
completes in one clock cycle. Working together, the 4X data bus and 2X address bus provide a data
bus bandwidth of up to 5.3 GB (677 MHz) per second. Finally, the FSB is also used to deliver
interrupts.
the “front side bus” in this document. The FSB utilizes a split-transaction, deferred reply protocol.
The FSB uses Source-Synchronous Transfer (SST) of address and data to improve performance.
The processor transfers data four times per bus clock (4X data transfer rate). Along with the 4X
data bus, the address bus can deliver addresses two times per bus clock and is referred to as a
‘double-clocked’, ‘double-pumped’, or the 2X address bus. In addition, the Request Phase
completes in one clock cycle. Working together, the 4X data bus and 2X address bus provide a data
bus bandwidth of up to 5.3 GB (677 MHz) per second. Finally, the FSB is also used to deliver
interrupts.
1.1
Terminology
A ‘#’ symbol after a signal name refers to an active low signal, indicating that a signal is in the
asserted state when driven to a low level. For example, when RESET# is low (i.e. when RESET# is
asserted), a reset has been requested. Conversely, when NMI is high (that is, when NMI is
asserted), a nonmaskable interrupt request has occurred. In the case of signals where the name does
not imply an active state but describes part of a binary sequence (such as address or data), the ‘#’
symbol implies that the signal is inverted. For example, D[3:0] = ‘HLHL’ refers to a hex ‘A’, and
D[3:0]# = ‘LHLH’ also refers to a hex ‘A’ (H= High logic level, L= Low logic level).
asserted state when driven to a low level. For example, when RESET# is low (i.e. when RESET# is
asserted), a reset has been requested. Conversely, when NMI is high (that is, when NMI is
asserted), a nonmaskable interrupt request has occurred. In the case of signals where the name does
not imply an active state but describes part of a binary sequence (such as address or data), the ‘#’
symbol implies that the signal is inverted. For example, D[3:0] = ‘HLHL’ refers to a hex ‘A’, and
D[3:0]# = ‘LHLH’ also refers to a hex ‘A’ (H= High logic level, L= Low logic level).
“Front side bus” refers to the interface between the processor, system core logic (i.e. the chipset
components), and other bus agents. The FSB supports multiprocessing and cache coherency. For
this document, “front side bus” is used as the generic term for the “Dual-Core Intel Xeon processor
7000 series system bus”.
components), and other bus agents. The FSB supports multiprocessing and cache coherency. For
this document, “front side bus” is used as the generic term for the “Dual-Core Intel Xeon processor
7000 series system bus”.
Commonly used terms are explained here for clarification:
•
FC-mPGA4 — The Dual-Core Intel Xeon processor 7000 series is available in a Flip-Chip
Micro Pin Grid Array 4 package, consisting of a processor core mounted on a pinned substrate
with an integrated heat spreader (IHS). This packaging technology employs a 1.27 mm [0.05
in] pitch for the substrate pins.
Micro Pin Grid Array 4 package, consisting of a processor core mounted on a pinned substrate
with an integrated heat spreader (IHS). This packaging technology employs a 1.27 mm [0.05
in] pitch for the substrate pins.
•
Front Side Bus (FSB) — The electrical interface that connects the processor to the chipset.
Also referred to as the processor system bus or the system bus. All memory and I/O
Also referred to as the processor system bus or the system bus. All memory and I/O
Table 1-1. Features of the Dual-Core Intel
®
Xeon
®
Processor 7000 Series
Processor
# of Supported
Symmetric
Agents per Bus
L2 Advanced
Transfer
Cache
Front Side Bus
Frequency
Package
Dual-Core Intel Xeon
processor 7000 series
processor 7000 series
1 - 2
1-2 MB per core
667 MHz
604-pin FC-mPGA4