Intel Xeon 7130N LF80550KF0878M Data Sheet
Product codes
LF80550KF0878M
Electrical Specifications
16
Dual-Core Intel
®
Xeon
®
Processor 7000 Series Datasheet
The BCLK[1:0] inputs directly control the operating speed for the FSB interface. The processor
core frequency is configured during reset by using values stored internally during manufacturing.
The stored value sets the highest bus fraction at which the particular processor can operate. If lower
speeds are desired, the appropriate ratio can be configured by setting bits [15:8] of the
IA32_FLEX_BRVID_SEL_MSR.
core frequency is configured during reset by using values stored internally during manufacturing.
The stored value sets the highest bus fraction at which the particular processor can operate. If lower
speeds are desired, the appropriate ratio can be configured by setting bits [15:8] of the
IA32_FLEX_BRVID_SEL_MSR.
Clock multiplying within the processor is provided by the internal phase locked loop (PLL), which
requires a constant frequency BCLK[1:0] input, with exceptions for spread spectrum clocking.
Processor DC and AC specifications for the BCLK[1:0] inputs are provided in
requires a constant frequency BCLK[1:0] input, with exceptions for spread spectrum clocking.
Processor DC and AC specifications for the BCLK[1:0] inputs are provided in
. The
Dual-Core Intel Xeon processor 7000 series utilizes differential clocks. Details regarding
BCLK[1:0] driver specifications are provided in the CK409 Clock Synthesizer/Driver Design
Guidelines or CK409B Clock Synthesizer/Driver Design Guidelines.
BCLK[1:0] driver specifications are provided in the CK409 Clock Synthesizer/Driver Design
Guidelines or CK409B Clock Synthesizer/Driver Design Guidelines.
frequency to FSB multipliers and their corresponding core frequencies.
2.1.2
Front Side Bus Clock Select (BSEL[1:0])
The BSEL[1:0] signals are hardwired outputs used to select the frequency of the processor input
clock (BCLK[1:0]).
clock (BCLK[1:0]).
defines the possible combinations of the signals and the frequency
associated with each combination. The required frequency is determined by the processor, chipset,
and clock synthesizer. All processors must operate at the same FSB frequency.
and clock synthesizer. All processors must operate at the same FSB frequency.
The Dual-Core Intel Xeon processor 7000 series operates at 667 MHz FSB frequency (selected by
a 166 MHz BCLK[1:0] frequency, respectively). Individual processors operate at the FSB
frequency specified by BSEL[1:0].
a 166 MHz BCLK[1:0] frequency, respectively). Individual processors operate at the FSB
frequency specified by BSEL[1:0].
For more information about these pins, refer to
and the appropriate platform design
guide.
Table 2-1. Core Frequency to Front Side Bus Multiplier Configuration
Core Frequency to
Front Side Bus Multiplier
Core Frequency with 166 MHz
Front Side Bus Clock
Notes
1/14
RESERVED
1, 2,
3
NOTES:
1. Individual processors operate only at or below the frequency marked on the package.
2. Listed frequencies are not necessarily committed production frequencies.
3. For valid core frequencies of the processor, refer to the Dual-Core Intel
1. Individual processors operate only at or below the frequency marked on the package.
2. Listed frequencies are not necessarily committed production frequencies.
3. For valid core frequencies of the processor, refer to the Dual-Core Intel
®
Xeon
®
Processor 7000 Sequence
Specification Update.
1/15
RESERVED
1/16
2.66 GHz
1/17
RESERVED
1/18
3 GHz
Table 2-2. BSEL[1:0] Frequency Table for BCLK[1:0]
BSEL1
BSEL0
Function
0
0
RESERVED
0
1
RESERVED
1
0
RESERVED
1
1
166 MHz