Intel Xeon 7130N LF80550KF0878M Data Sheet

22

The ODTEN signals enables or disables R

TT

. Those signals affected by ODTEN still present R

TT

 

termination to the signal’s pin when the processor is placed in tri-state mode.

Furthermore, the following signals are not affected when the processor is placed in tri-state mode: 
BSEL[1:0], SKTOCC#, SM_ALERT#, SM_CLK, SM_DAT, SM_EP_A[2:0], SM_TS_A[1:0], 
SM_WP, TEST_BUS, TESTHI[6:0], VID[5:0], TDO and VTTEN.

The Dual-Core Intel Xeon processor 7000 series does not utilize CMOS voltage levels on any 
signals that connect to the processor silicon. As a result, input signals such as A20M#, 
FORCEPR#, IGNNE#, INIT#, LINT0/INTR, LINT1/NMI, SMI#, SLP#, and STPCLK# utilize 
GTL input buffers.  Legacy output THERMTRIP# utilizes a GTL+ output buffers.  All of these 
Asynchronous GTL+ signals follow the same DC requirements as GTL+ signals, however the 
outputs are not driven high (during the logical 0-to-1 transition) by the processor.  FERR#/PBE#, 
IERR#, and IGNNE# have now been defined as AGTL+ asynchrnous signals as they include an 
active p-MOS device. GTL+ asynchronous and AGTL+ asynchronous signals do not have setup or 
hold time specifications in relation to BCLK[1:0].  However, all of the GTL+ asynchronous and 
AGTL+ asynchronous signals are required to be asserted/deasserted for at least six BCLKs in order 
for the processor to recognize them.  See 

 for the DC specifications for the asynchronous 

GTL+ signal groups.

NOTES:
1.  Signals not included in the “Signals with R

TT

” list require termination on the baseboard. Please refer to 

 for the signal type and 

 for the corresponding DC specifications.

A[39:3]#, ADS#, ADSTB[1:0]#, AP[1:0]#, BINIT#, BNR#, BOOT_SELECT

2

, BPRI#, D[63:0]#, DBI[3:0]#, 

DBSY#, DEFER#, DP[3:0]#, DRDY#, DSTBN[3:0]#, DSTBP[3:0]#, FORCEPR#, HIT#, HITM#, LOCK#, 
MCERR#, ODTEN

3

, REQ[4:0]#, RS[2:0]#, TEST_BUS, RSP#, TCK

4

, TDI

4

, TMS

4

, TRDY#, TRST#

4

2.  The BOOT_SELECT pin is not terminated with R

TT

. It has a 250-5000 

Ω internal pullup.

3.  THe ODTEN pin is not terminated with R

TT

. It has a 2 K

Ω -10 KΩ internal pullup.

4.  TCK, TDI, TMS and TRST# are not terminated with R

TT

. They have a 4 K

Ω-20 KΩ internal pullup.

BINIT#, BNR#, HIT#, HITM#, MCERR#

A20M#, A[39:3]#, ADS#, ADSTB[1:0]#, AP[1:0]#, 
BINIT#, BNR#, BPM[5:0]#, BPRI#, BR[3:0]#, 
D[63:0]#, DBI[3:0]#, DBSY#, DEFER#, DP[3:0]#, 
DRDY#, DSTBN[3:0]#, DSTBP[3:0]#, FORCEPR#, 
HIT#, HITM#, IGNNE#, INIT#, LINT0/INTR, 
LINT1/NMI, LOCK#, MCERR#, ODTEN, REQ[4:0]#, 
RESET#, RS[2:0]#, RSP#, SMI#, STPCLK#, TRDY#

BOOT_SELECT, PWRGOOD

1

, TCK

, TDI

, TMS

TRST#

1

, VIDPWRGD

NOTES:
1.  These signals also have hysteresis added to the reference voltage. See 

 for more information.